1. Dec 2010VLSI Interconnects 1 Instructed by Shmuel Wimer Eng. School, Bar-Ilan University Credits: David Harris Harvey Mudd College (Some material copied/taken/adapted from Harris’ lecture notes)

2. Dec 2010VLSI Interconnects 2 Outline  Introduction  Wire Resistance  Wire Capacitance  Wire RC Delay  Crosstalk  Wire Engineering  Repeaters  Scaling

3. Dec 2010VLSI Interconnects 3 Introduction  Chips are mostly made of wires called interconnect  Alternating layers run orthogonally

4. Dec 2010VLSI Interconnects 4  Transistors are little things under the wires  Many layers of wires

5. Dec 2010VLSI Interconnects 5  Wires are as important as transistors –Speed –Power –Noise

6. Dec 2010VLSI Interconnects 6 Wire Geometry  Pitch = w + s  Aspect ratio: AR = t/w –Old processes had AR << 1 –Modern processes have AR  2 Pack in many skinny wires l ws t h

7. Dec 2010VLSI Interconnects 7 Layer Stack  Modern processes use 6-10+ metal layers  Example: Intel 180 nm process  M1: thin, narrow (< 3 ) –High density cells  M2-M4: thicker –For longer wires  M5-M6: thickest –For V DD, GND, clk 61720860 2.0 51600800 2.0 41080540 2.0 3700320 2.2 2700320 2.2 Substrate 1480250 1.9 LayerT(nm) AR W (nm) S

8. Dec 2010VLSI Interconnects 8 Wire Resistance   = resistivity (  *m)  R  = sheet resistance (  /  ) –  is a dimensionless unit(!)  Count number of squares –R = R  * (# of squares) l w t 1 Rectangular Block R = R (L/W)  4 Rectangular Blocks R = R (2L/2W)  = R (L/W)  t l ww l

9. Dec 2010VLSI Interconnects 9 Choice of Metals  Until 180 nm generation, most wires were aluminum  Modern processes use copper –Cu atoms diffuse into silicon and damage FETs –Must be surrounded by a diffusion barrier Metal Bulk resistivity (  *cm) Silver (Ag)1.6 Copper (Cu)1.7 Gold (Au)2.2 Aluminum (Al)2.8 Tungsten (W)5.3 Molybdenum (Mo)5.3

10. Dec 2010VLSI Interconnects 10 Sheet Resistance  Typical sheet resistances in 180 nm process Layer Sheet Resistance (  /  ) Diffusion (silicided)3-10 Diffusion (no silicide)50-200 Polysilicon (silicided)3-10 Polysilicon (no silicide)50-400 Metal10.08 Metal20.05 Metal30.05 Metal40.03 Metal50.02 Metal60.02

11. Dec 2010VLSI Interconnects 11 Contacts Resistance  Contacts and vias also have 2-20   Use many contacts for lower R –Many small contacts for current crowding around periphery

12. Dec 2010VLSI Interconnects 12 Wire Capacitance  Wire has capacitance per unit length –To neighbors –To layers above and below  C total = C top + C bot + 2C adj layer n+1 layer n layer n-1 C adj C top C bot ws t h 1 h 2

13. Dec 2010VLSI Interconnects 13 Capacitance Trends  Parallel plate equation: C =  A/d –Wires are not parallel plates, but obey trends –Increasing area (W, t) increases capacitance –Increasing distance (s, h) decreases capacitance  Dielectric constant –  = k  0   0 = 8.85 x 10 -14 F/cm  k = 3.9 for SiO 2  Processes are starting to use low-k dielectrics –k  3 (or less) as dielectrics use air pockets

14. Dec 2010VLSI Interconnects 14 M2 Capacitance Data  Typical wires have ~ 0.2 fF/  m –Compare to 2 fF/  m for gate capacitance  Capacitance increases with metal planes above and below  Capacitance decreases with spacing

15. Dec 2010VLSI Interconnects 15 Diffusion & Polysilicon  Diffusion capacitance is very high (about 2 fF/  m) –Comparable to gate capacitance –Diffusion also has high resistance –Avoid using diffusion (and polysilicon) runners for wires!  Polysilicon has lower C but high R –Use for transistor gates –Occasionally for very short wires between gates

16. Dec 2010VLSI Interconnects 16 Lumped Element Models  Wires are a distributed system –Approximate with lumped element models  3-segment  -model is accurate to 3% in simulation

17. Dec 2010VLSI Interconnects 17

18. Dec 2010VLSI Interconnects 18

19. Dec 2010VLSI Interconnects 19 RC Example  Metal2 wire in 180 nm process –5 mm long –0.32  m wide  Construct a 3-segment  -model –R  = 0.05  /  => R = 781  –C permicron = 0.2 fF/  m => C = 1 pF 260  167 fF 260  167 fF 260  167 fF

20. Dec 2010VLSI Interconnects 20

21. Dec 2010VLSI Interconnects 21 Wire RC Delay Example  Estimate the delay of a 10x inverter driving a 2x inverter at the end of the 5mm wire from the previous example –R = 2.5 k  *  m for gates –Unit inverter: 0.36  m nMOS, 0.72  m pMOS –t pd = 1.1 ns 781  500 fF Wire 4 fF LoadDriver 690 

22. Dec 2010VLSI Interconnects 22 Crosstalk  A capacitor does not like to change its voltage instantaneously  A wire has high capacitance to its neighbor. –When the neighbor switches from 1→ 0 or 0→ 1, the wire tends to switch too. –Called capacitive coupling or crosstalk  Crosstalk effects –Noise on non switching wires –Increased delay on switching wires

23. Dec 2010VLSI Interconnects 23 Miller Effect  Assume layers above and below on average are quiet –Second terminal of capacitor can be ignored –Model as C gnd = C top + C bot  Effective C adj depends on behavior of neighbors –Miller effect B VV C eff(A) MCF ConstantV DD C gnd + C adj 1 Switching with A 0C gnd 0 Switching opposite A 2V DD C gnd + 2 C adj 2 AB C adj C gnd C Delay and power increase

24. Dec 2010VLSI Interconnects 24 Crosstalk Noise  Crosstalk causes noise on non switching wires  If victim is floating: –model as capacitive voltage divider C adj C gnd-v Aggressor Victim  V aggressor  V victim

25. Dec 2010VLSI Interconnects 25 Driven Victims  Usually victim is driven by a gate that fights noise –Noise depends on relative resistances –Victim driver is in linear region, agg. in saturation –If sizes are same, R aggressor = 2-4 x R victim C adj C gnd-v Aggressor Victim  V aggressor  V victim R aggressor R victim C gnd-a

26. Dec 2010VLSI Interconnects 26 Coupling Waveforms  Simulated coupling for C adj = C victim Aggressor Victim (undriven): 50% Victim (half size driver): 16% Victim (equal size driver): 8% Victim (double size driver): 4% t (ps) 020040060080010001200140018002000 0 0.3 0.6 0.9 1.2 1.5 1.8

27. Dec 2010VLSI Interconnects 27 Noise Implications  So what if we have noise?  If the noise is less than the noise margin, nothing happens  Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes –But glitches cause extra delay –Also cause extra power from false transitions  Dynamic logic never recovers from glitches  Memories and other sensitive circuits also can produce the wrong answer

28. Dec 2010VLSI Interconnects 28 Wire Engineering

29. Dec 2010VLSI Interconnects 29  Goal: achieve delay, area, power goals with acceptable noise  Degrees of freedom: –Width –Spacing –Layer –Shielding vdda 0 a 1 gnda 2 vddb 0 a 1 a 2 b 2 a 0 a 1 gnda 2 a 3 vddgnda 0 b 1

30. Dec 2010VLSI Interconnects 30 Repeaters  R and C are proportional to l  RC delay is proportional to l 2 –Unacceptably great for long wires  Break long wires into N shorter segments –Drive each one with an inverter or buffer Wire Length: l DriverReceiver l/N Driver Segment Repeater l/N Repeater l/N ReceiverRepeater N Segments

31. Dec 2010VLSI Interconnects 31 Repeater Design  How many repeaters should we use?  How large should each one be?  Equivalent Circuit –Wire length l Wire Capacitance C w *l, Resistance R w *l –Inverter width W (nMOS = W, pMOS = 2W) Gate Capacitance C’*W, Resistance R/W R/W C'WC w l /2NC w l R w l /N

32. Dec 2010VLSI Interconnects 32

33. Dec 2010VLSI Interconnects 33 w/o repeater k=1 Showing that repeater insertion pays small

34. Dec 2010VLSI Interconnects 34 Under what condition repeater insertion should take place?

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38. Dec 2010VLSI Interconnects 38 Cascaded driver with non-repeated interconnect Non-repeated interconnect The method is useful when R tr is dominant and C int is large

39. 39 v u, q Optimal Buffer Insertion ? ? ? ? ? ? ?

40. 40 Delay Model R3R3 C1C1 R2R2 R6R6 R5R5 R4R4 R7R7 C6C6 C5C5 C4C4 C7C7 R1R1 C2C2 C3C3 0 1 3 2 4 5 6 7

41. 41 Bottom-Up Solution RKRK CKCK K (T’ K, L’ K ) RMRM CMCM M sub-tree (T M, L M ) RNRN CNCN N sub-tree (T N, L N ) (T K, L K )

42. Dec 2010VLSI Interconnects 42 Scaling

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46. Dec 2010VLSI Interconnects 46 Scaling