1. 1 Registers & Counters Logic and Digital System Design - CS 303 Erkay Savaş Sabancı University

2. 2 Registers Registers are clocked sequential circuits A register is a group of flip-flops –Each flip-flop capable of storing one bit of information –An n-bit register consists of n flip-flops capable of storing n bits of information –besides flip-flops, a register usually contains combinational logic to perform some simple tasks –In summary flip-flops to hold information combinational logic to control the state transition

3. 3 Counters A counter is essentially a register that goes through a predetermined sequence of states “Counting sequence” RegisterFF 0 FF 1 FF n-1 Combinational logic

4. 4 Uses of Registers and Counters Registers are useful for storing and manipulating information –internal registers in microprocessors to manipulate data Counters are extensively used in control logic –PC (program counter) in microprocessors

5. 5 4-bit Register REG Q3Q3 Q2Q2 Q1Q1 Q0Q0 D3D3 D2D2 D1D1 D0D0 clear D Q clock C R D Q C R D Q C R D Q C R clear D0D0 D1D1 D2D2 D3D3 Q0Q0 Q1Q1 Q2Q2 Q3Q3 FD16CE 16 D[15:0] Q[15:0] CE C CLR

6. 6 Register with Parallel Load Load D Q C R Q0Q0 D Q C R Q1Q1 D Q C R Q2Q2 D Q C R Q3Q3 clock clear D1D1 D2D2 D3D3 D0D0

7. 7 Register Transfer 1/2 R1R1 R2R2 n load clock load clock R 2  R 1 R1R1 010…10110…11 010…10 R2R2

8. 8 Register Transfer 2/2 R 1  R 1 + R 2 clock R1R1 R2R2 n n-bit adder n load

9. 9 Shift Registers A register capable of shifting its content in one or both directions –Flip-flops in cascade serial input serial output D Q C SI D Q C D Q C D Q C SO clock The current of n-bit shift register state can be transferred in n clock cycles

10. 10 Serial Mode A digital system is said to operate in serial mode when information is transferred and manipulated one bit a time. shift register Ashift register B SO SI SO clk clock shift control clock shift control clk T1T1 T2T2 T3T3 T4T4

11. 11 Serial Transfer Suppose we have two 4-bit shift registers 11011101 After T 4 After T 3 After T 2 After T 1 01001101initial value Shift register BShift register ATiming pulse B  A clock shift control clk T1T1 T2T2 T3T3 T4T4 A B clock shift control

12. 12 Serial Addition In digital computers, operations are usually executed in parallel, since it is faster Serial mode is sometimes preferred since it requires less equipment shift register A shift register B SI FA a b C_in S C DQ C SO SI serial input clock shift control reset serial output

13. Example: Serial Addition 13 A and B are 2-bit shift registers clock 0 1010 0 00 shift control SR-A SR-B C_in 01

14. How to Write Inputs to Registers? 14 shift register A shift register B SI FA a b C_in S C DQ C SO SI serial input clock shift control reset serial output

15. 15 Example: Serial Addition A and B are 2-bit shift registers reset clock 010 01 0101010010101 serial input 000 1010 SR-A SR-B C_in 00 shift control

16. 16 Universal Shift Register Capabilities: 1.A “clear” control to set the register to 0. 2.A “clock” input 3.A “shift-right” control 4.A “shift-left” control 5.n input lines & a “parallel-load” control 6.n parallel output lines

17. 17 4-Bit Universal Shift Register D Q C D Q C D Q C D Q C A0A0 A1A1 A2A2 A3A3 parallel outputs clear clk 4  1 MUX 0 1 23 4  1 MUX 0 1 23 4  1 MUX 0 1 23 4  1 MUX 0 1 23 s1s1 s0s0 serial input for shift-right serial input for shift-left parallel inputs

18. 18 Universal Shift Register Mode Control Register operation s1s1 s0s0 00No change 01Shift right 10Shift left 11Parallel load

19. 19 Counters registers that go through a prescribed sequence of states upon the application of input pulses –input pulses are usually clock pulses Example: n-bit binary counter –count in binary from 0 to 2 n -1 Classification 1.Synchronous counters flip-flops receive the same common clock as the pulse 2.Ripple counters flip-flop output transition serves as the pulse to trigger other flip-flops

20. 20 Binary Ripple Counter 00 0 0 10 0 1 20 1 0 30 1 1 41 0 0 51 0 1 61 1 0 71 1 1 00 0 0 3-bit binary ripple counter Idea: –to connect the output of one flip-flop to the C input of the next high-order flip-flop We need “complementing” flip-flops –We can use T flip-flops to obtain complementing flip-flops or –JK flip-flops with its inputs are tied together or –D flip-flops with complement output connected to the D input.

21. 21 4-bit Binary Ripple Counter T Q C R A0A0 T Q C R A1A1 T Q C R A2A2 T Q C R A3A3 clear count logic-1 D Q C R A0A0 D Q C R A1A1 D Q C R A2A2 D Q C R A3A3 clear count 00 0 10 0 0 1 20 0 1 0 30 0 1 1 40 1 0 0 50 1 60 1 1 0 70 1 1 1 81 0 0 0 91 0 0 1 10 111 0 1 1 121 1 0 0 131 1 0 1 141 1 1 0 151 1 00 0

22. 22 4-bit Binary Ripple Counter –Suppose the current state is 1100 –What is the next state? T Q C R A0A0 T Q C R A1A1 T Q C R A2A2 T Q C R A3A3 clear count logic-1

23. 23 Synchronous Counters There is a common clock –that triggers all flip-flops simultaneously –If T = 0 or J = K = 0 the flip-flop does not change state. –If T = 1 or J = K = 1 the flip-flop does change state. Design procedure is so simple –no need for going through sequential logic design process –A 0 is always complemented –A 1 is complemented when A 0 = 1 –A 2 is complemented when A 0 = 1 and A 1 = 1 –so on 00 0 0 10 0 1 20 1 0 30 1 1 41 0 0 51 0 1 61 1 0 71 1 1 00 0 0

24. 24 4-bit Binary Synchronous Counter J Q C A0A0 J Q C A1A1 J Q C A2A2 J Q C A3A3 K K K K clock Count_enable to next stage Polarity of the clock is not essential

25. Timing of Synchronous Counters 25 A0A0 clock A3A3 A1A1 A2A2

26. Timing of Ripple Counters 26 A0A0 clock A3A3 A1A1 A2A2

27. 27 Up-Down Binary Counter When counting downward –the least significant bit is always complemented (with each clock pulse) –A bit in any other position is complemented if all lower significant bits are equal to 0. –For example: 0 1 0 0 Next state: –For example: 1 1 0 0 Next state: 00 0 0 71 1 1 61 1 0 51 0 1 41 0 0 30 1 1 20 1 0 10 0 1 00 0 0

28. 28 Up-Down Binary Counter The circuit T Q C A0A0 T Q C A1A1 T Q C A2A2 C clock up down

29. 29 Binary Counter with Parallel Load J Q C A0A0 J Q C A1A1 J Q C A2A2 K K K clock clear count load D0D0 D1D1 D2D2 carry output

30. 30 Binary Counter with Parallel Load clearclockloadCountFunction 0XXXclear to 0 1  1Xload inputs 1  01count up 1  00no change Function Table

31. 31 Other Counters Ring Counter –A ring counter is a circular shift register with only one flip-flop being set at any particular time, all others are cleared. shift right T0T0 T1T1 T2T2 T3T3 initial value 1000 Usage –Timing signals control the sequence of operations in a digital system

32. 32 Ring Counter Sequence of timing signals clock T0T0 T1T1 T2T2 T3T3

33. 33 Ring Counter To generate 2 n timing signals, –we need a shift register with ? flip-flops or, we can construct the ring counter with a binary counter and a decoder 2x4 decoder T0T0 T1T1 T2T2 T3T3 2-bit counter count Cost: 2 flip-flops 2-to-4 line decoder Cost in general case: n flip-flops n-to-2 n line decoder 2 n n-input AND gates n NOT gates

34. 34 Johnson Counter A k-bit ring counter can generate k distinguishable states The number of states can be doubled if the shift register is connected as a switch-tail ring counter clock D Q C D Q C D Q C D Q C X X’ Y Y’ Z Z’ T T’

35. 35 Johnson Counter Count sequence and required decoding S 7 = Z’T S 6 = Y’Z S 5 = X’Y S 4 = XT S 3 = ZT’ S 2 = YZ’ S 1 = XY’ S 0 = X’T’0000 8 7 6 5 4 3 2 1 TZYX Output Flip-flop outputssequence number

36. 36 Johnson Counter Decoding circuit S0S0 S1S1 S2S2 S3S3 S4S4 S5S5 S6S6 S7S7 clock D Q C D Q C D Q C D Q C X Y Z T

37. 37 Unused States in Counters 4-bit Johnson counter 0000 10001100 1110 111101110011 0001 0010 10010100 1010 110101101011 0101

38. 38 Correction 0000 10001100 1110 111101110011 0001 0010 1001 0100 1010 110101101011 0101

39. 39 Johnson Counter 0100 1010 10101101 11010110 01101011 10110101 01010010 00001001 10010100 Next StatePresent State 00001000 10001100 11001110 11101111 11110111 01110011 00110001 00010000 TZYXTZYX

40. 40 K-Maps ZT XY00011110 0011 0111 1111 1011 X(t+1) = T’ ZT XY00011110 00 01 111111 101011 Y(t+1) = XY + XZ + XT’ ZT XY00011110 00 011111 111111 10 Z (t+1) = Y ZT XY00011110 0011 0111 1111 1011 T (t+1) = Z

41. 41 Unused States in Counters Remedy D Y = X(Y+Z+T’) X(t+1) = T’ Y(t+1) = XY + XZ + XT’ Z(t+1) = YT(t+1) = Z clock Z T D Q C D Q C D Q C D Q C X Y