1. Nov 10, 2008ECE 561 Lecture 151 Adders

2. Nov 10, 2008ECE 561 Lecture 152 Adders Basic Ripple Adders Faster Adders Sequential Adders

3. Nov 10, 2008ECE 561 Lecture 153 The Half Adder Half Adder Input is limited to 2 bits –HS = X xor Y – = XY’ + X’Y –CO = XY Time for the Half Adder? –1 gate delay –A gate delay of an xor for the half sum –A gate delay of an AND gate for the carry out

4. Nov 10, 2008ECE 561 Lecture 154 The Full Adder Input is now A B and the Carry in. So have –S = X xor Y xor Cin – =XY’Cin’+X’YCin’+X’Y’Cin+XYCin –Cout = XY + XCin + YCin

5. Nov 10, 2008ECE 561 Lecture 155 The logic Two level logic Output delay –A, B Cin  Sum –Delay through 2 xor gates –t s = 2 t xor –A, B Cin  Cout –Delay through an AND gate and an OR gate –t Cout = t and + t or

6. Nov 10, 2008ECE 561 Lecture 156 Higher order symbol When using full adders in a circuit it becomes too cluttered if all gates are shown Use a symbol for the unit

7. Nov 10, 2008ECE 561 Lecture 157 Multiple Bit adders There are multiple approaches Most Basic is the Ripple adder –You can also do as good as a ripple adder –One figure of merit to evaluate is the area*time product –In a ripple adder the number of gates (area) grows linearly with the number of bits and the time also grow linearly.

8. Nov 10, 2008ECE 561 Lecture 158 The Ripple Adder Basic structure Delay for n bits t ADD = t XYCout + (n-2)t CinCout + t CinS

9. Nov 10, 2008ECE 561 Lecture 159 And in gate delays t ADD = t XYCout + (n-2)t CinCout + t CinS Where t XYCout = t and + t or + (n-2) (t and + t or ) + t xor = (n-1) (t and + t or ) + t xor As number of bits goes up time increases linearlly. Number of gates increases linearly.

10. Nov 10, 2008ECE 561 Lecture 1510 Which is more important factor? Usually time is the more important factor for an add. Why? –It is on the critical part for the instruction cycle time in any computer. –Why has it become more important today? –Address space has increased, programs are larger  more bits in program counter.

11. Nov 10, 2008ECE 561 Lecture 1511 How to add faster The most significant Sum bit of the adder is a function of all the inputs. Could just do a straight logic equation for each Sum bit as a function of all the bits of which it is a function. Or use a methodology That methodology is called carry- lookahead

12. Nov 10, 2008ECE 561 Lecture 1512 Carry-Lookahead Adders Start by defining two functions –Generate g i = x i y i –Propogate p i = x i + y i –And c i+1 = g i + p i c i or (expanding out) Having p i and g i, can now write the carry output of a stage – c 1 = g 0 + p 0 c 0 – c 2 = g 1 + p 1 c 1 = g 1 + p 1 (g 0 + p 0 c 0 ) – = g 1 + p 1 g 0 + p 1 p 0 c 0

13. Nov 10, 2008ECE 561 Lecture 1513 CLA continued – c 3 = g 2 + p 2 c 2 – = g 2 + p 2 (g 1 + p 1 g 0 + p 1 p 0 c 0 ) – = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0 – c 4 = g 3 + p 3 c 3 – = g 3 + p 3 (g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0 ) – = g 3 +p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 c 0 – And this can continue for as many bits as you want.

14. Nov 10, 2008ECE 561 Lecture 1514 The logic Implementing into gates

15. Nov 10, 2008ECE 561 Lecture 1515 Analysis Had our time for 4 bit addition from a ripple adder. Here the slowest bit is the msb output as it has the largest logic function. Multiple input gates are slower than 2 input gates. Start with the time for the propagate and generate signal logic – t pg = max(t and, t or )

16. Nov 10, 2008ECE 561 Lecture 1516 Analysis cont Now must generate s4 output t s4 = t pg + t or4 + t and4 + t xor Assume that 4 input gate is ½ the speed of 2 input and gate Assume xor time is 1.5 the speed of and ~= 5.5 t and + t pg If t and ~= t or time is ~= 6.5 t and versus a time of ~2 n t and for a ripple adder where is the number of bits

17. Nov 10, 2008ECE 561 Lecture 1517 In terms of gates A full adder takes 6 2-input gates –An n-bit ripple adder will take 6n gates The Carry Lookahead Adder –1 st stage 5 gates (max of 2 input) –2 nd state 7 gates (max of 2 input) –3 rd stage 8 gates (max of 3 input) –4 th stage 9 gates (max of 4 input) As you use more stage the area grows exponentially if you limit the number of inputs to the gates

18. Nov 10, 2008ECE 561 Lecture 1518 Tradeoff The ripple adder versus the carry look- ahead adder is a classic time and area tradeoff. In many circuits you can reduce time by using more logic to produce the output more directly.

19. Nov 10, 2008ECE 561 Lecture 1519

20. Nov 10, 2008ECE 561 Lecture 1520