1. 1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

2. 2 Fault Modeling

3. 3 Why Model Faults? I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments

4. 4 Functional Vs Structural Testing Consider testing of a ten-input AND function We apply an input pattern 0101010101 Output is 0 More than one inferences possible Functional test is necessary for verification The purpose of manufacturing test is to find any faults caused due to manufacturing defects

5. 5 Common Fault Models Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults

6. 6 Stuck-at Fault The circuit is modeled as an interconnection of Boolean gates Each connecting line can have two types of faults  Stuck-at-1 (s-a-1) & Stuck-at-0 (s-a-0)  A circuit with n lines can have 3^n-1 possible stuck line combinations  An n-line circuit can have at most 2n single stuck-at faults

7. 7 Single Stuck-at Fault Three properties define a single stuck-at fault Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults a b c d e f 1 0 g h i 1 s-a-0 j k z 0(1) 1(0) 1 Test vector for h s-a-0 fault Good circuit value Faulty circuit value

8. 8 Fault Equivalence Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fan-out branches). Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.

9. 9 Equivalence Rules sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 AND NAND OR NOR WIRE NOT FANOUT

10. 10 Equivalence Example sa0 sa1 Faults removed by equivalence collapsing 20 Collapse ratio = ----- = 0.625 32

11. 11 Fault Dominance If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list. When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example. If two faults dominate each other then they are equivalent.

12. 12 Dominance Example s-a-1 F1 s-a-1 F2 001 110 010 000 101 100 011 All tests of F2 Only test of F1 s-a-1 s-a-0 A dominance collapsed fault set

13. 13 Dominance Example sa0 sa1 Faults in blue removed by equivalence collapsing 15 Collapse ratio = ----- = 0.47 32 Faults in green removed by dominance collapsing

14. 14 Dominance Fault Collapsing An n-input Boolean gate requires (n+1) single stuck-at faults to be modeled. To collapse faults of a gate, all faults from the output can be eliminated retaining one type (s-a-1 for AND and NAND; S-A-0 for OR and NOR) of fault on each input and the other type (s-a-0 for AND and NAND; s-a-1 for OR and NOR) on any one of the inputs The output faults of the NOT gate, and the wire can be removed as long as both faults on the input are retained.

15. 15 Multiple Stuck-at Faults A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3 k -1. A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. Statistically, single fault tests cover a very large number of multiple faults.

16. 16 Transistor (Switch) Faults MOS transistor is considered an ideal switch and two types of faults are modeled: Stuck-open -- a single transistor is permanently stuck in the open state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage. Detection of a stuck-open fault requires two vectors. Detection of a stuck-short fault requires the measurement of quiescent current (I DDQ ).

17. 17 Stuck-Open Example Two-vector s-op test can be constructed by ordering two s-at tests A B V DD C pMOS FETs nMOS FETs Stuck- open 1010 0000 01(Z) Good circuit states Faulty circuit states Vector 1: test for A s-a-0 (Initialization vector) Vector 2 (test for A s-a-1)

18. 18 Stuck-Short Example A B V DD C pMOS FETs nMOS FETs Stuck- short 1010 0 (X) Good circuit state Faulty circuit state Test vector for A s-a-0 I DDQ path in faulty circuit

19. 19 Basic Principle of I DDQ Testing –Measure I DDQ current through V ss bus

20. 20 DFT

21. 21 DFT

22. 22 SCAN DESIGN We already know this!

23. 23 BIST Motivation Useful for field test and diagnosis (less expensive than a local automatic test equipment) Software tests for field test and diagnosis:  Low hardware fault coverage  Low diagnostic resolution  Slow to operate Hardware BIST benefits:  Lower system test effort  Improved system maintenance and repair  Improved component repair  Better diagnosis

24. 24 Costly Test Problems Alleviated by BIST Increasing chip logic-to-pin ratio – harder observability Increasingly dense devices and faster clocks Increasing test generation and application times Increasing size of test vectors stored in ATE Expensive ATE needed for 1 GHz clocking chips Hard testability insertion – designers unfamiliar with gate- level logic, since they design at behavioral level In-circuit testing no longer technically feasible Shortage of test engineers Circuit testing cannot be easily partitioned

25. 25 Typical Quality Requirements 98% single stuck-at fault coverage 100% interconnect fault coverage Reject ratio – 1 in 100,000

26. 26 BIST Architecture

27. 27 Economics – BIST Costs  Chip area overhead for: Test controller Hardware pattern generator Hardware response compacter Testing of BIST hardware  Pin overhead -- At least 1 pin needed to activate BIST operation  Performance overhead – extra path delays due to BIST  Yield loss – due to increased chip area or more chips In system because of BIST  Reliability reduction – due to increased area  Increased BIST hardware complexity – happens when BIST hardware is made testable

28. 28 BIST Benefits Faults tested:  Single combinational / sequential stuck-at faults  Delay faults  Single stuck-at faults in BIST hardware BIST benefits  Reduced testing and maintenance cost  Lower test generation cost  Reduced storage / maintenance of test patterns  Simpler and less expensive ATE  Can test many units in parallel  Shorter test application times  Can test at functional system speed

29. 29 Pattern Generation Store in ROM – too expensive Exhaustive Pseudo-exhaustive Pseudo-random (LFSR) – Preferred method Binary counters – use more hardware than LFSR Modified counters Test pattern augmentation  LFSR combined with a few patterns in ROM

30. 30 Pseudo-Random Pattern Generation Standard Linear Feedback Shift Register (LFSR)  Produces patterns algorithmically – repeatable  Has most of desirable random # properties Need not cover all 2 n input combinations Long sequences needed for good fault coverage

31. 31 Matrix Equation for Standard LFSR X 0 (t + 1) X 1 (t + 1). X n-3 (t + 1) X n-2 (t + 1) X n-1 (t + 1) 10...00h110...00h1 01...00h201...00h2 00...00100...001 …… …………… ……… 0. 1 0 h n-2 0. 0 1 h n-1 X 0 (t) X 1 (t). X n-3 (t) X n-2 (t) X n-1 (t) = X (t + 1) = T s X (t) (T s is companion matrix)

32. 32 LFSR Implements a Galois Field  Galois field (mathematical system):  Addition operator is XOR (  )  T s companion matrix:  1 st column 0, except nth element which is always 1 (X 0 always feeds X n-1 )  Rest of row n – feedback coefficients h i  Rest is identity matrix I – means a right shift Near-exhaustive (maximal length) LFSR  Cycles through 2 n – 1 states (excluding all-0)  1 pattern of n 1’s, one of n-1 consecutive 0’s 

33. 33 Standard n-Stage LFSR Implementation Autocorrelation – any shifted sequence same as original in 2 n-1 – 1 bits, differs in 2 n-1 bits If h i = 0, that XOR gate is deleted

34. 34 Example of LFSR Clock tickQ0Q1Q2 Q0Q1Q2 11117 20113 30011 41004 50102 61015 71106 81117

35. 35 Example of LFSR S0S1S2 100 010 101 110 111 011 001 100

36. 36 LFSR Theory Cannot initialize to all 0’s – hangs If X is initial state, progresses through states X, T s X, T s 2 X, T s 3 X, … Described by characteristic polynomial: f (x) = |T s – I X | = 1 + h 1 x + h 2 x 2 + … + h n-1 x n-1 + x n

37. 37 Example External XOR LFSR Characteristic polynomial f (x) = 1 + x + x 3 (read taps from right to left)

38. 38 External XOR LFSR Pattern sequence for example LFSR (earlier): Always have 1 and x n terms in polynomial Never repeat an LFSR pattern more than 1 time –Repeats same error vector, cancels fault effect X 0 (t + 1) X 1 (t + 1) X 2 (t + 1) 001001 101101 010010 X 0 (t) X 1 (t) X 2 (t) = X0X1X2X0X1X2 100100 001001 010010 101101 011011 111111 110110 100100 001001 …

39. 39 Generic Modular LFSR

40. 40 Modular Internal XOR LFSR Described by companion matrix T m = T s T Internal XOR LFSR – XOR gates in between D flip-flops Equivalent to standard External XOR LFSR  With a different state assignment  Faster – usually does not matter  Same amount of hardware X (t + 1) = T m x X (t) f (x) = | T m – I X | = 1 + h 1 x + h 2 x 2 + … + h n-1 x n-1 + x n

41. 41 Modular LFSR Matrix X 0 (t + 1) X 1 (t + 1) X 2 (t + 1). X n-3 (t + 1) X n-2 (t + 1) X n-1 (t + 1) 001...000001...000 000...010000...010 010...000010...000 ……… ……………… ……… 000...001000...001 1 h 1 h 2. h n-3 h n-2 h n-1 X 0 (t) X 1 (t) X 2 (t). X n-3 (t) X n-2 (t) X n-1 (t) = 000...000000...000

42. 42 Example Modular LFSR f (x) = 1 + x 2 + x 7 + x 8 Read LFSR tap coefficients from left to right

43. 43 VHDL Implementation

44. 44 VHDL Implementation signal lfsr_reg : std_ulogic_vector(9 downto 0); begin process (clock) variable lfsr_tap : std_ulogic; begin if clock'EVENT and clock='1' then if reset = '1' then lfsr_reg '1'); else lfsr_tap := lfsr_reg(6) xor lfsr_reg(9); lfsr_reg <= lfsr_reg(8 downto 0) & lfsr_tap; end if; end process; data_out <= lfsr_reg; end modular