1. Asynchronous vs. Synchronous Counters Ripple Counters Deceptively attractive alternative to synchronous design style State transitions are not sharp! Can lead to "spiked outputs" from combinational logic decoding the counter's state Can lead to "spiked outputs" from combinational logic decoding the counter's state Count signal ripples from left to right

2. Lect 15-2 Asynchronous vs. Synchronous Counters Cascaded Synchronous Counters with Ripple Carry Outputs First stage RCO enables second stage for counting RCO asserted soon after stage enters state 1111 also a function of the T Enable Downstream stages lag in their 1111 to 0000 transitions Affects Count period and decoding logic (1) Low order 4-bits = 1111 (2) RCO goes high (3) High order 4-bits are incremented + + PTPT PTPT DCBADCBA count clk DCBADCBA DCBADCBA QD QC QB QA QD QC QB QA LOAD HGFEHGFE CLR RCO

3. Lect 15-3 The Power of Synchronous Clear and Load Starting Offset Counters: e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110,... Use RCO signal to trigger Load of a new state Since 74163 Load is synchronous, state changes only on the next rising clock edge 0110 is the state to be loaded D C B A L O A D C L R R C O PT Q A Q B Q C Q D 1 6 3 Load D C B A 01 ++ Asynchronous vs. Synchronous Counters CLKCLK

4. Offset Counters Continued Ending Offset Counter: e.g., 0000, 0001, 0010,..., 1100, 1101, 0000 Decode state to determine when to reset to 0000 Clear signal takes effect on the rising count edge Replace '163 with '161, Counter with Async Clear Clear takes effect immediately! Asynchronous vs. Synchronous Counters

5. Lect 15-5 Memory technology types  Read-Only Memory (ROM)  Non-volatile storage  ROM, PROM, EPROM, EEPROM  Random Access Memory (RAM)  Static RAM (SRAM)  Dynamic RAM (DRAM)

6. Lect 15-6 ROM types  OT-PROM (one time programmable)  Mask ROM  Fuse ROM  PROM  EPROM  EEPROM Word Line Bit Line Mask ROM Fuse ROM Word Line Bit Line Word Line Bit Line EPROM EEPROM Flash Memory Floating gate

7. Lect 15-7 SRAM  Hold data without external refresh  Simplicity : don ’ t require external refresh circuitry  Speed: SRAM is faster than DRAM  Cost: several times more expensive than DRAMs  Size: take up much more space than DRAMs  Power: consume more power than DRAMs  Usage: level 1 or level 2 cache Word Line Bit Line Word Line Bit Line

8. Lect 15-8 Random Access Memories Static RAM Transistor efficient methods for implementing storage elements Small RAM: 256 words by 4-bit Large RAM: 4 million words by 1-bit We will discuss a 1024 x 4 organization Static RAM Cell Words = Rows Columns = Bits (Double Rail Encoded)

9. Lect 15-9 Random Access Memories Static RAM Organization Chip Select Line (active lo) Write Enable Line (active lo) 10 Address Lines 4 Bidirectional Data Lines

10. Lect 15-10 Random Access Memories RAM Organization Long thin layouts are not the best organization for a RAM 64 x 64 Square Array Amplifers & Mux/Demux Some Addr bits select row Some Addr bits select within row

11. Lect 15-11 Random Access Memories RAM Timing Simplified Read Timing Simplified Write Timing

12. Lect 15-12 Random Access Memories Dynamic RAMs Word Line Bit Line 1 Transistor (+ capacitor) memory element Read: Assert Word Line, Sense Bit Line Write: Drive Bit Line, Assert Word Line Destructive Read-Out Need for Refresh Cycles: storage decay in ms Internal circuits read word and write back

13. Lect 15-13 Random Access Memories Long rows to simplify refresh Two new signals: RAS, CAS Row Address Strobe Column Address Strobe replace Chip Select DRAM Organization

14. Random Access Memory RAS, CAS Addressing Even to read 1 bit, an entire 64-bit row is read! Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits! Read Cycle Read Row Row Address Latched Read Bit Within Row Column Address Latched Tri-state Outputs

15. Lect 15-15 Random Access Memory Write Cycle Timing (1) Latch Row Address Read Row (2) WE low (3) CAS low: replace data bit (4) RAS high: write back the modified row (5) CAS high to complete the memory cycle

16. Random Access Memory RAM Refresh Refresh Frequency: 4096 word RAM -- refresh each word once every 4 ms Assume 120ns memory access cycle This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)! But RAM is really organized into 64 rows This is one refresh cycle every 62.5  s (1 in 500 DRAM accesses) Large capacity DRAMs have 256 rows, refresh once every 16  s RAS-only Refresh (RAS cycling, no CAS cycling) External controller remembers last refreshed row Some memory chips maintain refresh row pointer CAS before RAS refresh: if CAS goes low before RAS, then refresh

17. Lect 15-17 DRAM Technologies  Conventional DRAM  Fast Page Mode (FPM) DRAM  Extended Data Out (EDO) DRAM  Synchronous DRAM (SDRAM)  Double Data Rate SDRAM (DDR SDRAM)  Direct Rambus DRAM (DRDRAM)  Synchronous-Link DRAM (SLDRAM)

18. Lect 15-18 Fast Page Mode (FPM) DRAM  Sending the row address just once for many accesses to memory in locations near each other, improving access time  Page mode  Burst mode access  Memory is not read one byte at a time (32 or 64 bits at a time)  Several consecutive chunks of memory  “x-y-y-y” for four consecutive accesses

19. Lect 15-19 Synchronous DRAM  Tied to the system clock  Burst mode  System timing : 5-1-1-1  Internal interleaving  New memory standard for modern PCs  Speed  Access time: 10ns, 12ns,…  MHz rating: 100 MHz, 133MHz

20. Lect 15-20 Synchronous DRAM, cont’d  Latency  SDRAMs are still DRAMs  5-1-1-1 (10ns means the second, third and fourth access times)  2-clock and 4-clock Circuitry  2-clock: 2 different DRAM chips on the module  4-clock: 4 different DRAM chips  Packaging  Usually comes in DIMM packaging  Buffered and unbuffered, 3.3 V and 5.0V

21. Lect 15-21 SDRAM DIMM  64Mx64 SDRAM DIMM based on 32Mx8, 4 banks 3.3v SDRAMs with SPD  SPD: serial presence detect chip: speed and design information about the module

22. Lect 15-22 Direct Rambus DRAM (DRDRAM)  Direct Rambus channel  High speed 16-bit bus, 400MHz  Transfers at rising and falling edges, 1.6Gbytes/second  Rambus Inline Memory module (RIMM)

23. Lect 15-23 Synchronous-Link DRAM (SLDRAM)  SLDRAM Consortium  Evolutionary design  64bit bus running at a 200 MHz clock speed (effective speed of 400 MHz)  3.2 Gbytes/second  Open standard

24. Lect 15-24 Chapter Summary The Variety of Sequential Circuit Packages Registers, Shifters, Counters, RAMs Counters as Simple Finite State Machines Counter Design Procedure 1. Derive State Diagram 2. Derive State Transition Table 3. Determine Next State Functions 4. Remap Next State Functions for Target FF Types Using Excitation Tables; Implement Logic Different FF Types in Counters J-K best for reducing gate count in packaged logic D is easiest design plus best for reducing wiring and area in VLSI Asynchronous vs. Synchronous Counters Avoid Ripple Counters! State transitions are not sharp Beware of potential problems when cascading synchronous counters Offset counters: easy to design with synchronous load and clear Never use counters with asynchronous clear for this kind of application