1. 1 ASIC 120: Digital Systems and Standard-Cell ASIC Design Tutorial 1: Introduction to Digital Circuits January 25, 2006

2. 2 Outline Digital Systems Digital Design and its relation to ASICs Combinational Logic –NOT, AND, OR, XOR, NAND, etc. –mux, half-adder, full-adder Sequential Logic –flip-flop/register, shift register, counter

3. 3 Digital Systems Analog vs. Digital –continuously varying vs. discrete –imprecise vs. precise –0..1 vs. 0 or 1 Digital systems excel at… –repetitive calculations –large amounts of data –reproducible results

4. 4 Digital Systems Implemented in integrated circuits (ICs) mounted on a printed circuit board (PCB)

5. 5 The Big Picture

6. 6

7. 7 Components of a Digital System Printed circuit board (PCB) Embedded software –microprocessor –microcontroller –digital signal processor (DSP) ASIC Programmable Logic Device (PLD) –FPGA, etc.

8. 8 ASICs Application Specific Integrated Circuit –from a user perspective, implies integrated circuit with a specific application –from a design perspective, implies any integrated circuit Since we are designers, ASICs include –SRAMs –phase locked loops (PLLs) –microprocessors –analog-to-digital converters –FPGAs –etc.

9. 9 Consider an ASIC Physically comprised of –Package –Pins –Silicon wafer metal interconnect layers insulating layers vias at the bottom, transistors resting on a silicon substrate

10. 10 Consider an ASIC: Package

11. 11 Consider an ASIC: Side View Source:Figure 3-11 from ECE 438 textbook (Rabaey, Jan M., Anantha Chandrakasan, Borivoje Nikolić, “Digital Integrated Circuits: A Design Perspective,” 2 nd Edition; Pearson Education: New Jersey, 2003.)

12. 12 Consider an ASIC: Substrate Source:Figure 3-13 from ECE 438 textbook (Rabaey et al., “Digital Integrated Circuits,” 2 nd Edition)

13. 13 Consider an ASIC Conceptually –System –Module –Gate –Circuit –Device Source:Figure 1-6 from ECE 438 textbook (Rabaey et al., “Digital Integrated Circuits,” 2 nd Edition)

14. 14 FPGAs Field Programmable Gate Array –part of the Complex Programmable Logic Device (CPLD) family of PLDs –essentially reprogrammable hardware FPGAs can be very small or very big –clock rates over 1 GHz –implement multiple 32-bit processors

15. 15 Components of an FPGA Logic Elements (LEs) Routing Input/Output logic Extra features –clocking –memory –memory interfaces –multipliers

16. 16 The Logic Element Two main parts –Look-Up Table (LUT) for combinational logic –Flip Flop (FF) for sequential logic (memory)

17. 17 Top Level View of an FPGA

18. 18 Top Level View of an FPGA

19. 19 Digital ASIC/FPGA Design Flow Dependent on target environment, process, resources available, etc. Generic flow: 1.System architecture 2.Register Transfer Level (RTL) high level, synthesizable, optimized functional simulation, timing simulation 3.Synthesis more simulation 4.Manufacturing testing

20. 20 Register Transfer Level (RTL) This is where we start –schematic –hardware description languages (VHDL, etc.)

21. 21 Combinational and Sequential Logic We can break a digital system into two types of logic Combinational –computation happens in a linear fashion Sequential –computation involves a feedback loop (memory)

22. 22 RTL and Combinational/Sequential Logic Register Clock Cloud of Logic Register Cloud of Logic Data In Data Out Feedback Combinational Sequential

23. 23 Combinational Logic: NOT AX 01 10 InputOutput Truth Table Boolean algebra expression: X = A

24. 24 Combinational Logic: AND ABX 000 010 100 111 Boolean algebra expressions:X = A  B X = AB

25. 25 Combinational Logic: OR ABX 000 011 101 111 Boolean algebra expression:X = A + B

26. 26 Combinational Logic: XOR ABX 000 011 101 110 Boolean algebra expression:X = A  B

27. 27 Combinational Logic: NAND ABX 001 011 101 110 Boolean algebra expressions:X = A  B X = AB

28. 28 NAND: Transistor Schematic

29. 29 NAND: Transistor Layout vdd gnd

30. 30 Combinational Logic: NOR, XNOR ABX 001 010 100 110 ABX 001 010 100 111 X = A + B X = A  B

31. 31 Building Combinational Circuits ABCX 0000 0100 1001 1101 0010 0111 1010 1111 X = AC + BC

32. 32 Combinational Logic: MUX (multiplexer) ABCX 0000 0100 1001 1101 0010 0111 1010 1111 X = AC + BC

33. 33 Half Adder ABSC 0000 0110 1010 1101 S = A  B C = AB

34. 34 Full Adder S = A  B  Ci Co = AB + Ci(A  B)

35. 35 Full Adder

36. 36 Full Adder Application: 8-Bit Ripple-Carry Adder Constructed by connecting 8 full adders together A B Ci Co S A B Ci Co S A B Ci Co S A B Ci Co S A B Ci Co S A B Ci Co S A B Ci Co S A B Ci Co S 0 Carry Out A0A0 A1A1 A2A2 A3A3 A4A4 A5A5 A6A6 A7A7 B0B0 B1B1 B2B2 B3B3 B4B4 B5B5 B6B6 B7B7 S0S0 S1S1 S2S2 S3S3 S4S4 S5S5 S6S6 S7S7

37. 37 What I’ve Skipped Gates with more than two inputs Karnaugh maps Quine-McCluskey method Binary arithmetic, base conversions Practical digital circuits have more than 0s and 1s Transmission gates, tri-state buffers

38. 38 Sequential Logic

39. 39 Basic Feedback Element: SR Latch SRQQ next 0000 0011 1011 1001 0110 0100 110N/A 111

40. 40 Basic Feedback Element: SR Latch Simplified truth table: SRQ 00hold 101 (set) 010 (reset) 11invalid

41. 41 Basic Feedback Element: SR Latch 0 0 0 1 (Hold State)

42. 42 Basic Feedback Element: SR Latch 0 0 0 1 1 0 (Hold State)

43. 43 Basic Feedback Element: SR Latch 0 0 1 0 (Hold State)

44. 44 Basic Feedback Element: SR Latch 0 0 1 0 0 1 (Hold State)

45. 45 Basic Feedback Element: SR Latch 0 1 0 1 (Set State)

46. 46 Basic Feedback Element: SR Latch 0 1 0 1 1 0 (Set State)

47. 47 Basic Feedback Element: SR Latch 0 1 0 0 1 0 (Set State)

48. 48 Basic Feedback Element: SR Latch 0 1 0 0 0 0 (Set State)

49. 49 Basic Feedback Element: SR Latch 0 1 1 0 0 0 (Set State)

50. 50 Basic Feedback Element: SR Latch 0 1 1 0 0 1 (Set State)

51. 51 Basic Feedback Element: SR Latch 1 1 0 1 (Invalid State)

52. 52 Basic Feedback Element: SR Latch 1 1 0 1 1 0 (Invalid State)

53. 53 Basic Feedback Element: SR Latch 1 1 0 0 1 0 (Invalid State)

54. 54 Basic Feedback Element: SR Latch 1 1 0 0 0 0 (Invalid State)

55. 55 Basic Feedback Element: SR Latch Q and Q are supposed to have opposite (“complementary”) values –i.e., Q = Q In the invalid state (S = 1, R = 1) Q ≠ Q –should be avoided

56. 56 D Flip-Flop or Register DClkQQ next 0000 0011 1000 1011 0 0101 00 0 0101 10 1 0101 01 1 0101 11

57. 57 D Flip-Flop or Register Clock input controls when data output takes value of data input –triggered on either rising or falling edge of clock

58. 58 Latches vs. Flip-Flops Latches –no clock input –data output changes in response to data input –level-sensitive Flip-Flops –has clock input –data output changes in response to data input on rising or falling clock edge –edge-sensitive

59. 59 Synchronous vs. Asynchronous Synchronous –circuit operation governed by a clock –currently more popular and practical –flip-flops Asynchronous –circuit operation independent of a clock –potentially faster than synchronous –lower power consumption –difficult to design –latches

60. 60 Sequential Constructs Shift registers Counters State Machines (next tutorial)

61. 61 Shift Register Consider a series of D flip-flops (DFFs) connected in series, as a 4-bit shift register DFF D Q DFF D Q DFF D Q DFF D Q Clk Data In Data Out

62. 62 Shift Register DFF D Q DFF D Q DFF D Q DFF D Q Clk Data In Data Out 000 00 0

63. 63 Shift Register DFF D Q DFF D Q DFF D Q DFF D Q Clk Data In Data Out 100 00 0

64. 64 Shift Register DFF D Q DFF D Q DFF D Q DFF D Q Clk Data In Data Out 110 00  (1)

65. 65 Shift Register DFF D Q DFF D Q DFF D Q DFF D Q Clk Data In Data Out 010 00  (0)

66. 66 Shift Register DFF D Q DFF D Q DFF D Q DFF D Q Clk Data In Data Out 001 00  (1)

67. 67 Shift Register DFF D Q DFF D Q DFF D Q DFF D Q Clk Data In Data Out 000 10  (1)

68. 68 Shift Register DFF D Q DFF D Q DFF D Q DFF D Q Clk Data In Data Out 000 01  (1)

69. 69 Counters: Ring Counter Connect shift register output to input Add set and clear functionality to DFFs Clk DFF D Q S C DFF D Q S C DFF D Q S C DFF D Q S C Init

70. 70 Counters: Ring Counter Clk 010 00 DFF D Q S C DFF D Q S C DFF D Q S C DFF D Q S C Init 1

71. 71 Counters: Ring Counter Clk 010 00 DFF D Q S C DFF D Q S C DFF D Q S C DFF D Q S C Init 0

72. 72 Counters: Ring Counter Clk 001 00  (1) DFF D Q S C DFF D Q S C DFF D Q S C DFF D Q S C Init 0

73. 73 Counters: Ring Counter Clk 000 10  (1) DFF D Q S C DFF D Q S C DFF D Q S C DFF D Q S C Init 0

74. 74 Counters: Ring Counter Clk 100 01  (1) DFF D Q S C DFF D Q S C DFF D Q S C DFF D Q S C Init 0

75. 75 Counters: Ring Counter Clk 010 00 DFF D Q S C DFF D Q S C DFF D Q S C DFF D Q S C Init 0 Each DFF output is a digit in a binary number Sequence was:1000 (8) 0100 (4) 0010 (2) 0001 (1) 1000 (8) …  (1)

76. 76 T Flip-Flop Clock is the only input Output inverts on rising edge of the clock (or “toggle”) input

77. 77 Counters: Binary Counter Implemented using series of T flip-flops Counts 0000, 0001, 0010, 0011, etc. Clk Q T Q T Q T Q T

78. 78 Counters: Binary Counter Clk 00 00 Q T Q T Q T Q T

79. 79 Counters: Binary Counter Clk 10 00 Q T Q T Q T Q T  (1)

80. 80 Counters: Binary Counter Clk 01 00 Q T Q T Q T Q T  (1)

81. 81 Counters: Binary Counter Clk 11 00 Q T Q T Q T Q T  (1)

82. 82 Counters: Binary Counter Clk 00 10 Q T Q T Q T Q T  (1)

83. 83 Counters: Binary Counter Clk 10 10 Q T Q T Q T Q T  (1) and so on…

84. 84 State Machines Useful abstract constructs for more complex sequential logic More on these next time

85. 85 What I’ve Skipped Other flip-flops (RS, JK) Many other interesting sequential circuits (barrel shifters, gray counters, etc.)

86. 86 Hardware Description Languages (HDLs) HDL describes in text a digital circuit Examples –VHDL (we will look at this next time) –Verilog –AHDL –JHDL

87. 87 Hardware Description Languages (HDLs) schematics are useful for… –drawing high level diagrams –manually working out simple pieces of logic HDLs are useful for… –describing complex digital systems HDLs are not... –software programming languages (C, Java, assembly, etc.)

88. 88 Summary Digital Systems Digital Design and its relation to ASICs Combinational Logic –NOT, AND, OR, XOR, NAND, etc. –mux, half-adder, full-adder Sequential Logic –flip-flop/register, shift register, counter

89. 89 Next Tutorial State machines Tutorial 1 in VHDL Digital Design Thought Process –VHDL is not a programming language like C or Java –hardware entities represented using text

90. 90 UW ASIC Design Team www.asic.uwaterloo.ca Reference material –Bryce Leung’s tutorials (UW ASIC website) –Michael Goldsmith’s tutorials (UW ASIC website) –ECE 223, 427, 438 course notes & textbooks My contact info: Jeff Wentworth, j.wentworth@gmail.com