1. Glitches/Hazards and ALUs
Today:
First Hour: Glitches and Hazards
Section 3.4 of Katz’s Textbook
In-class Activity #1
Second Hour: ALU
Section 5.3 of Katz’s Textbook
In-class Activity #2

2. What are Glitches? Glitches are a kind of logic noise
They are unwanted transients that occur in otherwise steady-state waveforms
They are caused by propagation delays and timing defects in combinational logic circuits
Hence, they are called 'glitches' taken from the German word "Glitsche" meaning slip or error.
“Hazard” = potential glitch in a circuit

3. Kinds of Hazards Static Hazards
A glitch that occurs in a logically steady-state 0 or 1 output when a single input changes
A single input has a delay asymmetry in path to output
Static1-hazard (also called SOP hazard)
Static 0-hazard (also called POS hazard)
Dynamic Hazards
Multiple transition glitches that occur in a multilevel circuit
A single input has 3 or more delay asymmetries in path to output
Function Hazards
A glitch that occurs when 2 or more inputs to a gate change at (almost) the same time

4. Glitch Related Definitions
Coupled Variable
is complemented in one term of the output expression and uncomplemented in another
Coupled Term
has only one coupled variable
Residue
is that part of a coupled term that remains after removing the coupled variable
Hazard Cover (or Consensus term)
is the Redundant Prime Implicant (RPI) required to eliminate the static hazard

5. Example of Definitions
Consensus Theorem Forms
X is the coupled (complemented) variable
X Y and X' Z or (X + Y) and (X' + Z) are coupled terms
Y and Z are residues
and
Y ZSOP or (Y + Z)POS is the Redundant Prime Implicant (RPI)

6. Static Hazard Detection
Example: X = A' B + A C = (A' + C)(A + B) AB C
SOP Hazard:
Coupled variable = A
Coupled terms = A' B, A C
Residues = B, C
RPI = B C, hazard cover  X = A' B + A C + B C
When input of X changes, a glitch occurs because the circuit needs to switch over to a new prime implicant.
A B C  A' B C 

7. Static Hazard Detection
Example: X = A' B + A C = (A' + C)(A + B) AB C
POS Hazard:
Coupled variable = A
Coupled terms = A + B, A' + C
Residues = B, C
RPI = B + C, hazard cover  X = (A' + C)(A + B)(B + C)
Solution: add a RPI (circuit segment) based upon the consensus theorem so that the transition is is covered in the new prime implicant (circuit segment).
(A + B + C)  (A' + B + C) 

8. Glitch Procedure Identify the coupled SOP or POS terms
Add RPI consensus term(s)
The circuit will not longer be minimized
Reject any set of two terms containing more than one coupled variable
Read the initial and final states from the coupled terms in hazardous transition (i.e., minterms for SOP, Maxterms for POS)

9. 4 Variable Example - SOP SOP Hazards AB 00 01 11 10 00 0 1 1 0 CD AB CD
hazard cover

10. 4 Variable Example - POS POS Hazards AB 00 01 11 10 00 0 1 1 0 CD AB CD
hazard cover

11. Alternate Procedure Detect static 1-hazards in SOP expression for F
Add RPI(s) to obtain SOP hazard-free expression
Convert SOP-hazard free to POS for F’
Detect static 0-hazards in POS expression
Add RPI(s) to obtain POS hazard-free expression
Final expression is both static 1- and 0- hazard-free

12. Katz Alternative Method
4 Variable Example - Alt.
Katz Alternative Method
1. Get FSOP+
2. Look at (FSOP+)'
3. Check (FSOP+)' SOP and make 0-hazard free, if needed AB CD
0-hazard free

13. Apply glitch/hazard detection, elimination techniques
Do Activity #1 Now
Apply glitch/hazard detection, elimination techniques

14. Arithmetic Logic Unit ALU CONTROL INPUTS SIGNALS OUTPUTS Si-1 … S0 M
Bn-1 … B0
An-1 … A0
INPUTS
ALU
Fn-1 … F0 Cn
OUTPUTS

15. Sample ALU Specification
Logical and Arithmetic Operations S1 1 S0
Function
Fi = Ai
Fi = not Ai
Fi = Ai xor Bi
Fi = Ai xnor Bi
Comment
Input Ai transferred to output
Complement of Ai transferred to output
Compute XOR of Ai, Bi
Compute XNOR of Ai, Bi
M = 0, Logical Bitwise Operations
M = 1, C0 = 0, Arithmetic Operations (with no carry in) 1
F = A
F = not A
F = A plus B
F = (not A) plus B
Input A passed to output
Complement of A passed to output
Sum of A and B
Sum of B and complement of A
M = 1, C0 = 1, Arithmetic Operations (with carry in) 1
F = A plus 1
F = (not A) plus 1
F = A plus B plus 1
F = (not A) plus B plus 1
Increment A
Twos complement of A
Increment sum of A and B
B minus A
Not all operations appear useful, but "fall out" of internal logic

16. Sample ALU Bit Slice Design1 S1 S0 Ci X Ai Bi Fi
Ci+1 X 1 X 1 X X X 1 X 1 X X 1 X X X 1 X X
Traditional Design Approach:
Truth Table
S0, S1 = Select bits
M = Mode (arithmetic/logic)
Ai, Bi = Inputs
Ci = Carry in
Fi = Output
Ci+1 = Carry out 1 X 1 X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

17. Sample ALU Design Design Comparisons
1. espresso SOP implementation: 25 gates, 2 levels
2. MisII (a multilevel synthesis tool)
optimized implementation: 12 gates, 2 levels
3. Clever hand design: 8 gates, 4 levels (but uses XORs)

18. Clever Hand Design Implementation
Multilevel ALU Design
Clever Hand Design Implementation S1 Bi S0 Ai
S1 = 0  Bi is blocked
Then operations involve Ai only
S0 controls operation of X1
S0 = 0, X1 passes Ai
S0 = 1, X1 passes Ai'
The XOR gate acts as an invertering or non-inverting buffer
M = 0  Ci is blocked
This decouples the bit slices
M = 1  Carry in ripples thru
OR gate O1 output:
Ci+1 = Ai•Ci + Bi•(Ai  Ci)
XOR gate X3 output:
Fi = Ai  Bi  Ci M Ci X1 A1 A2
8 Gates
(3 are XOR) X2 A3 A4 X3 O1
Ci+1 Fi

19. Active High Inputs & Outputs, Active Low Carries
74181 TTL ALU
Active High Inputs & Outputs, Active Low Carries
Selection M = H, Logic M = L, Arithmetic Functions
S3 S2 S1 S0 Functions Cn = H Cn = L
L L L L A' A A plus 1
L L L H (A + B)' A + B (A + B) plus 1
L L H L A' B A + B' (A + B') plus 1
L L H H 0 minus 1 zero
L H L L (A B)' A plus A B' A plus A B' plus 1
L H L H B' (A + B) plus A B' (A + B) plus A B' plus 1
L H H L A  B A minus B minus 1 A minus B
L H H H A B' A B minus 1 A B
H L L L A' + B A plus A B A plus AB plus 1
H L L H (A  B)' A plus B A plus B plus 1
H L H L B (A + B') plus A B (A + B') plus A B plus 1
H L H H A B A B minus 1 A B
H H L L 1 A plus A = 2A 2A plus 1
H H L H A + B' (A + B) plus A (A + B) plus A plus 1
H H H L A + B (A + B') plus A (A + B') plus A plus 1
H H H H A A minus 1 A

20. 74181 ALU & 74182 Carry Lookahead Units
The sense of the carry in and carry out are OPPOSITE from the input bits (no bubbles)
181 A3 A2 A1 A0 B3 B2 B1 B0 Cn M S3 S2 S1 S0 F3 F2 F1 F0
A=B G P
Cn+4 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23
182 P3 P2 P1 P0 G3 G2 G1 G0
Cn+z
Cn+x
Cn+y 12
Fortunately, the carry lookahead generator maintains the correct sense of the signals

21. with Carry Lookahead Unit CLU speeds up calculations of multi-chip ALU
182 P3 P2 P1 P0 G3 G2 G1 G0 Cn
Cn+z
Cn+x P G
Cn+y 13 3 1 14 5 4 2 15 6 12 11 9 10 7
181 A3 A2 A1 A0 B3 B2 B1 B0 M S3 S2 S1 S0 F3 F2 F1 F0
A=B
Cn+4 8 16 17 18 19 20 21 22 23 C0
C16
16-bit ALU
Carry out
with Carry Lookahead Unit
Group G & P
CLU speeds up calculations of multi-chip ALU
Carry in

22. Do Activity #2 Now For Next Class: Due: End of Class Today
RETAIN THE LAST PAGE (#3)!!
For Next Class:
Bring Randy Katz Textbook, & TTL Data Book
Required Reading:
Sec 6.1 of Katz
This reading is necessary for getting points in the Studio Activity!