1. Carry look ahead adder P (I) = a(I) xor b(I); G(I) = a(I) and b(I); S(I) = p(I) xor c(I); Carry(I+1) = c(I)p(I) + g(I)

2. Carry vector C(0) = cin C(1) = c(0)p(0) + g(0) C(2) = c(0)p(0)p(1) + g(0)p(1)+g(1) C(3)=c(2)p(2) + g(2) =c(0)P(0)p(1)(p2)+g(0)p(1)p(2)+g(1)p(2)+g(2) C(4) = c(3)p(3) + g(3) =c(0)P(0)p(1)p(2)p(3)+g(0)p(1)p(2)p(3)+g(1)p(2)p(3)+g(2)p (3) + g(3)

4. VHDL code entity carrylookadder is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); cin : in std_logic; s : out std_logic_vector(3 downto 0); cout : out std_logic); end carrylookadder;

5. architecture Behavioral of carrylookadder is signal c:std_logic_vector(4 downto 0); signal p,g: std_logic_vector(3 downto 0); begin G1: for i in 3 downto 0 generate p(i) <= a(i) xor b(i);-- p is a sum of half adder g(i) <= a(i) and b(i);-- g is a carry of a half adder s(i) <= p(i) xor c(i);-- s is a sum of the full adder end generate; -------Carry look ahead array c(0) <= cin; c(1) <= (cin and p(0)) or g(0); -- c(1)<= c(0)and p(0) or g(0) c(2) <= (cin and p(0) and p(1)) or (g(0) and p(1)) or g(1);-- c(2)<= c(1)and p(1) or g(1); c(3) <= (cin and p(0) and p(1) and p(2)) or (g(0) and p(1) and p(2)) or (g(1) and p(2)) or g(2); --c(3)<=c(2)and p(2) or g(2) c(4) <= (cin and p(0) and p(1) and p(2) and p(3)) or (g(0) and p(1) and p(2) and p(3)) or (g(1) and p(2) and p(3)) or (g(2) and p(3)) or g(3); -- c(3) <= (c(2)and p(2)) or g(2) cout <= c(4);-- c(4) <= (c(3) and p(3)) or g(3) end Behavioral;

6. Result