1. Use CMOS Transistors to bit a 4-bit Adder

2. NAND2 symbol Schematic

3. Implementation of a Full Adder (ES210) (carry-in)

4. Full Adder 2 Half Adder – XOR – AND OR

5. NAND-Based XOR Gate schematic symbol

6. NAND-Based AND Gate schematic symbol

7. NAND-Based OR Gate schematic symbol

8. Full Adder Symbol

9. Test Bench For the Adder

10. Waveforms of the Full Adder

11. Four-Bit Adder C 4 is calculated last because it takes C 0 8 gates to reach C 4. Each FA uses 2 XOR, 2 AND and 1 OR gate. A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.

12. Test Bench in Verilog

13. Create Config

14. Use Template

15. AMS Simulator

16. Model Library Setup

17. Use the 5 V Connect Rules

18. Choose Enough Levels of Hierarchy to Save

19. Output of the 4-bit Adder Open database first!