1. Reconfigurable Computing - VHDL John Morris Chung-Ang University The University of Auckland

2. Resources  These notes  Will be available on the Web  Temporarily, you can download them from http://cs.auckland.ac.nz/~jmor159/reconfig http://cs.auckland.ac.nz/~jmor159/reconfig  I will arrange a local (CAU) site ASAP  ASAP = ‘as soon as possible’!  Other resources  Links will be available on the same web site  VHDL text  Any text on VHDL will be adequate!  Recommended P J Ashenden, …………… (A fellow Australian!)

3. Background  US Department of Defense ‘High Order Language’ project  Aim: One language for all defense needs  Result: Ada  Ada  General purpose programming language  Based on Pascal  Original Ada was not Object-Oriented  Ada’95 has OO capabilities  Named after Ada, Countess of Lovelace  Never write it ADA – it’s not an acronym!  But VHDL is one

4. VHDL  VHSIC Hardware Design Language  VHSIC = Very High Speed Integrated Circuit  Standardized  IEEE 1076-1987 (VHDL’87)  IEEE 1076-1993 (VHDL’93)  Note: Verilog did not achieve standardization until 199x  Based on Ada  Extensions added to support Hardware Design  VHDL compiler should accept simple Ada programs  Ada compiler should accept VHDL functions

5. VHDL - Basics  Case insensitive  Convention  Keywords in upper case BEGIN, END, ENTITY, ARCHITECTURE, LOOP, ….  Variables in lower case i, j, k, clock, …  Types in lower case integer, std_logic, std_logic_vector  This is just a convention – you can choose your own!  For these slides, I will use this font and colour  ENTITY adder IS …  for anything that you could type into a VHDL model

6. Assignment operator is := Type follows variable list Statement terminated by ; VHDL - Basics  Statements similar to Pascal  Variable declaration  x, y : integer;  Assigment  x := 5.0*y + 2;  Program blocks delimited by BEGIN … END;  Example PROCEDURE SQR( x: integer ) RETURNS integer IS VARIABLE z : integer; BEGIN z := x * x; RETURN z; END; VHDL is quite verbose (long winded!)

7. VHDL – Entities and Architectures  VHDL supports abstraction through  Entities  Defines interface for a module  Architectures  Implementation of a module  There may be several architectures corresponding to one entity Generally, there are several ways (circuits) that will produce the same result

8. VHDL – Entities  Example: n -bit adder ENTITY adder IS a, b : std_logic_vector; sum : std_logic_vector; carry_out : std_logic; END adder; adder 8 8 a b sum 8 carry_out There are several ways of Implementing an n-bit adder … but all have the same interface or ENTITY in VHDL

9. Architectures  An architecture contains the implementation details  At a high level, a designer is only interested in the interface – information which is contained in the VHDL ENTITY  Each ARCHITECTURE is associated with an ENTITY ENTITY adder IS … END adder; ARCHITECTURE ripple OF adder IS … END ripple; ARCHITECTURE c_select OF adder IS … END c_select; One entity One or more architectures

10. Architecture – Style  Styles of architecture  You can design a circuit in several ways  In VHDL, you can build a model for a circuit in several ways too!  Behavioural aDataflow bAlgorithmic  Structural

11. Architectures – Style example  Example  Consider a full adder:  Logic equations are: adder 1 1 a c_in sum 1 carry_out 1 b 1 sum := a xor b xor c; carry_out := (a and b) or (b and c) or (a and c); ENTITY full_adder IS a, b : std_logic; sum : std_logic; carry_out : std_logic; END adder;

12. Architectures – Dataflow style  Example  Consider a full adder:  Logic equations are:  Dataflow architecture is adder 1 1 a c_in sum 1 carry_out 1 b 1 sum := a xor b xor c; carry_out := (a and b) or (b and c) or (a and c); ENTITY full_adder IS a, b : IN std_logic; sum, carry_out : OUT std_logic; END full_adder;

13. Architectures – Behavioural (Dataflow ) style  Example  Consider a full adder:  Logic equations are:  Dataflow architecture is adder 1 1 a c_in sum 1 carry_out 1 b 1 sum := a xor b xor c; carry_out := (a and b) or (b and c) or (a and c); ENTITY full_adder IS a, b : IN std_logic; sum, carry_out : OUT std_logic; END full_adder; Note that these are signal assignments. Although they are similar to ordinary assignments (using :=), there are some important differences which we will consider soon! ARCHITECTURE df OF full_adder IS BEGIN sum <= a xor b xor c; carry_out <= (a and b) or (b and c) or (a and c); END df;

14. Architectures – Structural style  Example  Consider a full adder:  Logic equations are:  A Structural model builds a model from other models adder 1 1 a c_in sum 1 carry_out 1 b 1 sum := a xor b xor c; carry_out := (a and b) or (b and c) or (a and c); ENTITY full_adder IS a, b : IN std_logic; sum, carry_out : OUT std_logic; END full_adder;

15. Architectures – Structural style  Build basic models for internal elements:  xor  or  and  Build the full adder from these elements ENTITY xor IS a, b : IN std_logic; c : OUT std_logic; END xor; ENTITY or IS a, b : IN std_logic; c : OUT std_logic; END xor; ENTITY and IS a, b : IN std_logic; c : OUT std_logic; END xor;

16. Architectures – Structural style  Build basic models for internal elements:  xor  or  and  For these, the architectures are trivial ENTITY xor IS a, b : IN std_logic; c : OUT std_logic; END xor; ARCHITECTURE A OF xor IS c <= a xor b; END xor;

17. Instantiate a second xor circuit, label it x2 x2 Instantiate an xor circuit, label it x1 x1 Architectures – Structural style  Now you ‘wire up’ the basic elements to make the full adder circuit  Considering the sum part only a b c sum ab Map the signals in xor’s ENTITY to actual wires in this circuit ARCHITECTURE structural OF full_adder IS SIGNAL ab: std_logic; BEGIN x1: xor PORT MAP( a => a, b => b, c => ab ); x2: xor PORT MAP( a => ab, b => c, c => sum ); … -- or / and circuits to compute carry out END xor;

18. Architectures – Algorithmic style & mixtures  Algorithmic models can include any type of construct that you find in a high level language – if … then … else, case, loop, procedure calls, etc.  We will look at some examples of this style after we’ve reviewed VHDL statements  Note that styles can be mixed in one model  A structural style model may include some dataflow statements and some algorithmic blocks, etc.

19. Architectures – Architectural style  Exercise  Complete the structural model for a full adder by adding the `circuitry’ for the carry out signal  Write a (very short) paragraph describing how your additions to the full adder model work. If you do this, I will also try to help you improve your technical English by carefully correcting your paragraph. (Hopefully, if we start with some short, simple exercises, you will become much more fluent before the end of semester!)  Bring your exercise to the lecture on Tuesday morning.