2. Chapter 4: Gates and Circuits Chapter 4 Gates and Circuits Page 30 The AND Operation (i.e., are both operands “true”?) 1 AND 1 11 AND 0 00 AND 1 00 AND 0 010101001 AND 10011100 1000100000001111 AND 10110101 00000101 The OR Operation (i.e., is either operand “true”?) 1 OR 1 11 OR 0 10 OR 1 10 OR 0 010101001 OR 10011100 1011110100001111 OR 10110101 10111111 The following Boolean operations are easy to incorporate into circuitry and can form the building blocks of many more sophisticated operations… The NOT Operation (i.e., what’s the opposite of the operand’s value?) NOT 1 = 0 NOT 0 = 1 NOT 10101001 = 01010110 NOT 00001111 = 11110000

3. More Boolean Operators Chapter 4 Gates and Circuits Page 31 The NAND Operation (“NOT AND”) 1 NAND 1 01 NAND 0 10 NAND 1 10 NAND 0 110101001 NAND 10011100 0111011100001111 NAND 10110101 11111010 The NOR Operation (“NOT OR”) 1 NOR 1 01 NOR 0 00 NOR 1 00 NOR 0 110101001 NOR 10011100 0100001000001111 NOR 10110101 01000000 The XOR Operation (“Exclusive OR”, i.e, either but not both is “true”) 1 XOR 1 01 XOR 0 10 XOR 1 10 XOR 0 010101001 XOR 10011100 0011010100001111 XOR 10110101 10111010

4. Transistors Chapter 4 Gates and Circuits Page 32 Transistors are relatively inexpensive mechanisms for implementing the Boolean operators. In addition to the input connection (the base) Transistors are connected to both a power source and a voltage dissipating ground. Essentially, when the input voltage is high, an electric path is formed within the transistor that causes the power source to be drained to ground. When the input voltage is low, the path is not created, so the power source is not drained.

5. Using Transistors to Create Logic Gates Chapter 4 Gates and Circuits Page 33 A NOT gate is essentially implemented by a transistor all by itself. A NAND gate uses a slightly more complex setup in which both inputs would have to be high to force the power source to be grounded. A NOR gate grounds the power source if either or both of the inputs are high. Use the output of a NAND gate as the input to a NOT gate to produce an AND gate, Use the output of a NOR gate as the input to a NOT gate to produce an OR gate..

6. How to Use Logic Gates for Arithmetic Chapter 4 Gates and Circuits Page 34 ANDs and ORs are all well and good, but how can they be used to produce binary arithmetic? Let’s start with simple one-bit addition (with a “carry” bit just in case someone tries to add 1 + 1!). SumBitCarryBit 0+0=00 0+1=10 1+0=10 1+1=01 Result0XOR0=0 0XOR1=1 1XOR0=1 1XOR1=0Result0AND0=0 0AND1=0 1AND0=0 1AND1=1 Notice that the sum bit always yields the same result as the XOR operation, and the carry bit always yields the same result as the AND operation! By combining the right circuitry, then, multiple-bit addition can be implemented, as well as the other arithmetic operations.

7. Memory Circuitry Chapter 4 Gates and Circuits Page 35 With voltages constantly on the move, how can a piece of circuitry be used to retain a piece of information? In the S-R latch, as long as the S and R inputs remain at one, the value of the Q output will never change, i.e., the circuit serves as memory! To set the stored value to one, merely set the S input to zero (for just an instant!) while leaving the R input at one. To set the stored value to zero, merely set the R input to zero (for just an instant!) while leaving the S input at one. Question: What goes wrong if both inputs are set to zero simultaneously?

8. Integrated Circuits Chapter 4 Gates and Circuits Page 36 How does all of that elaborate circuitry get placed on the tiny microchips used in modern computers? A clean silicon wafer is oxidized to produce a thin layer of silicon dioxide, which is then coated with a radiation-sensitive film. The wafer is masked by lithography to expose it selectively to ultraviolet light, which causes the film layer to become dissolvable. Light-exposed areas are dissolved, exposing parts of the silicon dioxide layer, which are removed by an etching process. The remaining film is removed in a liquid bath. The areas of silicon exposed by the etching process are negatively charged by exposure to either arsenic or phosphorus vapor at high temperatures The areas covered by silicon dioxide remain positively charged. The silicon dioxide is removed The wafer is oxidized again. An opening is etched down to the positively charged silicon using a reverse mask. Another oxidation cycle forms a thin layer of silicon dioxide on the positively charged region of the wafer. Windows are etched in the negatively charged silicon areas in preparation for metal deposits.