1. claudio.talarico@mail.ewu.edu1 Computing Systems Designing a basic ALU

2. 2 Let’s start designing a processor !!!!  Almost ready to move into chapter 5 and start building a processor  First, let’s review Boolean Logic and build the ALU we’ll need (Material from Appendix B) 32 b operation result a ALU

3. 3 Review: Boolean algebra and gates Problem :  Consider a logic function with three inputs: A, B, and C.  Output D is true if at least one input is true  Output E is true if exactly two inputs are true  Output F is true only if all three inputs are true  Show the truth table for these three functions.  Show the Boolean equations for these three functions.  Show an implementation consisting of inverters, AND, and OR gates. ABCDEF 000000 001100 010100 011110 100100 101110 110110 111101 Solution D = A + B + C E = A’.B.C + A.B’.C+ A.B.C’ F = A.B.C

4. 4 one-bit adder a b carry in carry out sum Multiple bits can be cascaded It takes three input bits and generates two output bits

5. 5 one-bit adder: Boolean algebra c i = carry in, c o = carry out = c i+1, s = sum s = a’.b’.ci + a’.b.ci’+ a.b’.ci’ + a.b.ci = a xor b xor ci c i+1 = a.b + (a+b).c i when both a and b are 1 c i+1 is 1 no matter c i abcicos 00000 00101 01001 01110 10001 10110 11010 11111

6. 6 Ripple adder c0 a0b0 s0 c1 a1b1 s1 c2 a2b2 s2 c3 a n-1 b n-1 S n-1 cncn c n-1 … aibicici+1sigipi 0000000 0010100 0100100 0111001 1000100 1011001 1101010 1111110

7. 7 Ripple adder aibicici+1sigipi 0000000 0010100 0100100 0111001 1000100 1011001 1101010 1111110 gi = ai.bi pi = ai’.bi.ci + ai.bi’.ci = ci.(ai xor bi) xor gates can be very fast if designed using pass transistors si = pi* xor ci but: si = pi xor ci is not true ! si = pi** xor ci is not true ! It is more convenient to use pi* or pi** than pi ci+1 = gi + pi.ci = gi + ci.ci.(ai xor bi) = gi.ci.(ai xor bi) = gi + ci.pi* where pi* = ai xor bi or alternatively ci+1 = gi + pi**.ci with pi** = ai + bi and

8. 8 Ripple adder timing c0 a0b0 s0 c1 a1b1 s1 c2 a2b2 s2 c3 a n-1 b n-1 S n-1 cncn c n-1 … worst case: t adder = (n-1) t carry + t sum where: t carry = delay from c i to c i+1 t sum = delay from c n-1 to s n c i+1 = gi + pi*.ci si = pi* xor ci Assuming the sum circuit is slower than the carry otherwise simply: t adder = n t carry

9. 9 Problem: carry ripple adder is slow  Is there more than one way to do addition ?  two extremes: ripple carry and sum-of-products Can you see the ripple? How could you get rid of it? c 1 = b 0 c 0 + a 0 c 0 + a 0 b 0 c 2 = b 1 c 1 + a 1 c 1 + a 1 b 1 c 2 = c 3 = b 2 c 2 + a 2 c 2 + a 2 b 2 c 3 = c 4 = b 3 c 3 + a 3 c 3 + a 3 b 3 c 4 = … sum-of-product not feasible! Why? YES !!! we would need “infinite”hardware !!!

10. 10 Carry-lookahead adder  An approach in-between the two extremes (sum-of-products and ripple adders)  Motivation:  If we didn't know the value of carry-in, what could we do?  When would we always generate a carry? g i =a i b i  When would we propagate the carry? p i =a i +b i  How to get rid of the ripple?  for each bit in an n-bit adder: c i+1 = f(a i,b i,c i )= g i + p i c i  The dependency between c i+1 and c i can be eliminated by expanding c i (i.e., compute c i for each stage in parallel instead of waiting for the carry from the previous stage)

11. 11 Carry lookahead adder c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 c 2 = g 1 +p 1 g 0 +p 1 p 0 c 0 c 3 = g 2 + p 2 c 2 c 3 = g 2 +p 2 g 1 +p 2 p 1 g 0 +p 2 p 1 p 0 c 0 c 4 = g 3 + p 3 c 3 c 4 = g 3 +p 3 g 2 +p 3 p 2 g 1 +p 3 p 2 p 1 g 0 +p 3 p 2 p 1 p 0 c 0

12. 12 Building bigger adders  Can’t build a 16 bit CLA adder... (too big)  Solution: use the CLA principle recursively  We could use ripple carry of 4-bit CLA adders

13. 13 An ALU (arithmetic logic unit)  Let’s build an ALU to support add, and,or instructions  we'll just build a 1 bit ALU, and use 32 of them  Possible Implementation (sum-of-products):  Not easy to decide the “best” way to build something  Don't want too many inputs to a single gate  Don’t want to have to go through too many gates  for our purposes, ease of comprehension is important b a operation result opabres

14. 14 Building a 32-bit ALU

15. 15 What about subtraction (a – b) ?  Two's complement approach: just negate b and add.  How do we negate b? invert b and add 1 through the cin

16. 16 Adding the NOR instruction  How do we get a nor b ?  Can also choose to invert a De Morgan

17. 17 Tailoring the ALU to the MIPS  Need to support the set-on-less-than instruction (slt)  remember: slt is an arithmetic instruction  produces a 1 if rs < rt and 0 otherwise  use subtraction: (a-b) < 0 implies a < b  Need to support test for equality (beq $t5, $t6, $t7)  use subtraction: (a-b) = 0 implies a = b

18. 18 Supporting slt and detecting overflow Can we figure out the idea ? Use this ALU for most significant bit Use this ALU for all other bits

19. 19 Supporting slt

20. 20 Test for equality Notice control lines: 0000 = and 0001 = or 0010 = add 0110 = subtract 0111 = slt 1100 = nor Note: zero is a 1 when the result is zero!

21. 21 The ALU

22. 22 Conclusion  We can build an ALU to support the MIPS instruction set  key idea: use multiplexor to select the output we want  we can efficiently perform subtraction using two’s complement  we can replicate a 1-bit ALU to produce a 32-bit ALU  Important points about hardware  all of the gates are always working  the speed of a gate is affected by the number of inputs to the gate  the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”)  Our primary focus: comprehension, however,  Clever changes to organization can improve performance (similar to using better algorithms in software)  We saw this in multiplication, and addition

23. 23 Conclusion  Real processors use more sophisticated techniques for arithmetic  Where performance is not critical, hardware description languages allow designers to completely automate the creation of hardware!