1. Basic Overview of VHDL Matthew Murach Slides Available at: www.pages.drexel.edu/~mjm46

2. What is VHDL? VHDL is hardware descriptive language that is used to design and implement hardware devices. VHDL is hardware descriptive language that is used to design and implement hardware devices. VHDL is used in prototyping devices and in the development of hardware simulators. VHDL is used in prototyping devices and in the development of hardware simulators. Most of the concepts of VHDL design were covered in ECEC200 logic circuits. Most of the concepts of VHDL design were covered in ECEC200 logic circuits.

3. -- Property of Dr. Nagvajara Library ieee; Use ieee.std_logic_1164.all; Entity full_adder is Port (a, b, cin : in std_logic; cout, sum : out std_logic); cout, sum : out std_logic); End full_adder; Architecture behav of full_adder is Begin Process(a, b, cin) Begin SUM <= a xor b xor cin; SUM <= a xor b xor cin; COUT <= (a and b) or (b and cin) or (cin and a); COUT <= (a and b) or (b and cin) or (cin and a); End Process; End Behav; First Program – lecture notes

4. Fundamentals of VHDL Comments in VHDL use double hyphens just like the // in C++ Comments in VHDL use double hyphens just like the // in C++ For example For example -- This is a comment All Lines in VHDL similar to C++ terminate with the semicolon All Lines in VHDL similar to C++ terminate with the semicolon An important note is that VHDL is NOT case sensitive i.e. IF and if are both keywords. An important note is that VHDL is NOT case sensitive i.e. IF and if are both keywords.

5. Header of the VHDL Code Headers for the VHDL files are very analogous to headers in C++. A simple syntax for this header file is as follows Headers for the VHDL files are very analogous to headers in C++. A simple syntax for this header file is as follows Library ieee; -- Use IEEE defined libraries Use ieee.std_logic_1164.all;--Defines std logic type Use work.p1_pack.all;-- User Defined library

6. Entity Declaration Entity full_adder is Port (a, b, cin : in std_logic; cout, sum : out std_logic); cout, sum : out std_logic); End full_adder; Essentially the entity declaration declares the ports used by the device. In this case we are defining a full adder so we have three inputs a, b, and the carry in (cin). We have two outputs carry out (cout) and the sum. Essentially the entity declaration declares the ports used by the device. In this case we are defining a full adder so we have three inputs a, b, and the carry in (cin). We have two outputs carry out (cout) and the sum. std_logic is analogous to bool in C as it defines a boolean type ‘0’ or ‘1’ and other types such as ‘x’ don’t care. std_logic is analogous to bool in C as it defines a boolean type ‘0’ or ‘1’ and other types such as ‘x’ don’t care.

7. Architecture Section Architecture arch_name of entity_name is -- Signal declarations here BeginProcess(sensitivity_list) -- Variable declarations here Begin -- do something here End Process; End arch_name; This section defines how the hardware behaves and operates This section defines how the hardware behaves and operates Note that signal declarations should be made before beginning processes and variables are declared in the process. Note that signal declarations should be made before beginning processes and variables are declared in the process.

8. Architecture Section The sensitivity list includes all signals in which this device should operate namely when a change in the signal(s) occurs. The sensitivity list includes all signals in which this device should operate namely when a change in the signal(s) occurs. The process given in the example operates on a change in either a,b,cin The process given in the example operates on a change in either a,b,cin Normally you should use a clock to drive the process section Normally you should use a clock to drive the process section process(ck) – Trigger process on ck

9. Signals and Variables Note that in VHDL there are two types of assignment signals and variables. Note that in VHDL there are two types of assignment signals and variables. A variable is analogous to C++’s definition. A variable is analogous to C++’s definition. i.e. A := temp; -- A now equals temp’s value i.e. A := temp; -- A now equals temp’s value A Signal is analogous to real wiring. A Signal is analogous to real wiring. i.e A <= temp; – A equals temp AFTER delay i.e A <= temp; – A equals temp AFTER delay Use of signals over variables is STRONGLY encouraged. Use of signals over variables is STRONGLY encouraged.

10. Truth Table Logic Process(a, b, cin) Begin SUM <= a xor b xor cin; SUM <= a xor b xor cin; COUT <= (a and b) or (b and cin) or (cin and a); COUT <= (a and b) or (b and cin) or (cin and a); End Process; This section defines the logic behind the Full Adder device This section defines the logic behind the Full Adder device ABCISCO 00000 00110 01010 01101 10010 10101 11001 11111

11. -- Property of Dr. Nagvajara Library ieee; Use ieee.std_logic_1164.all; Entity full_adder is Port (a, b, cin : in std_logic; cout, sum : out std_logic); cout, sum : out std_logic); End full_adder; Architecture behav of full_adder is Begin Process(a, b, cin) Begin SUM <= a xor b xor cin; SUM <= a xor b xor cin; COUT <= (a and b) or (b and cin) or (cin and a); COUT <= (a and b) or (b and cin) or (cin and a); End Process; End Behav;