1. Nanowire systems: technology and design by Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, and Giovanni De Micheli Philosophical Transactions A Volume 372(2012):20130102 March 28, 2014 ©2014 by The Royal Society

2. Three-dimensional sketch of the SiNWFET featuring two independent gates and its associated symbol (a). Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

3. IDS–V CG logarithmic plot of a measured device for several V PG voltages. Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

4. Pseudo-logic XOR characteristic obtained using a single SiNWFET with controllable polarity [19]. Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

5. Two-input XOR (a) and XNOR (b) gates built with DG-SiNWFETs [7]. Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

6. Various implementations of the function. Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

7. Conceptual representation of a regular sea of tiles. Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

8. Dumbbell–stick diagram (a), transistor pairing (b), transistor grouping (c) and logic tile (d). Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

9. Schematic of a static two-input NAND gate (a) and its equivalent dumbbell–stick diagram (b). Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

10. Schematic of a static two-input XOR gate [7] (a) and its equivalent dumbbell–stick diagram (b). Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

11. D flip–flop mapped on a regular set of tiles [19]. Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

12. BBDD non-terminal node [31]. Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

13. BBDD node corresponding logic gate and realization in ambipolar and CMOS technologies [31]. Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

14. Transmission-gate three-input XOR (a), three-input majority logic gate (b) and generalized arithmetic gate (MUX-XNOR) (c). Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

15. Full-adder implementation with eight controllable polarity devices. Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society

16. Self-checking n-bit adder using carry-checking parity-prediction scheme [36]. Pierre-Emmanuel Gaillardon et al. Phil. Trans. R. Soc. A 2014;372:20130102 ©2014 by The Royal Society