1. Chapter 1_4 Part III more on … Counters Chapter 1_4 Part III more on … Counters

2. Correction (slide no. 34) 4-Bit Binary Counter with Parallel Loop Load

3. Overview Part 1 - Registers, Microoperations and Implementations Part 1 - Registers, Microoperations and Implementations Registers and load enable Registers and load enable Register transfer operations Register transfer operations Microoperations - arithmetic, logic, and shift Microoperations - arithmetic, logic, and shift Microoperations on a single register Microoperations on a single register Multiplexer-based transfers Multiplexer-based transfers Shift registers Part 2 - Counters, register cells, buses, & serial operations Part 2 - Counters, register cells, buses, & serial operations Microoperations on single register (continued) Microoperations on single register (continued) Counters Counters Register cell design Register cell design Multiplexer and bus-based transfers for multiple registers Multiplexer and bus-based transfers for multiple registers Serial transfers and microoperations Serial transfers and microoperations

4. Two Counter Categories 1. Ripple counters (Asynchronous counter) 2. Synchronous counter

5. Ripple Counters

6. 4-bit Binary Ripple Counter

7. A 2-bit Asynchronous (ripple) Binary Counter Both flip-flops are assumed to be initially RESET (Q low). Both flip-flops are assumed to be initially RESET (Q low). Q 0 is always the LSB unless otherwise specified. Q 0 is always the LSB unless otherwise specified. Both J and K inputs are tied to logic “1”. Both J and K inputs are tied to logic “1”.

8. Timing diagram for the 2-bit Asynchronous Binary Counter This is a complete timing diagram & propagation delay time is not indicated. This is a complete timing diagram & propagation delay time is not indicated. Overall timing diagram - normally omitted for simplicity but it is very important in design & troubleshooting purposes Overall timing diagram - normally omitted for simplicity but it is very important in design & troubleshooting purposes

9. JK Flip-flop Characteristic

10. Binary State Sequence for the 2-bit Asynchronous Binary Counter CLOCK PULSE Q1Q0 Initially00 101 210 311 4 (recycles) 00

11. CLOCK PULSE Q1Q0Initially00 101 210 311 4 (recycles) 00

12. How about the … 3-bits Counter?

13. A 3-bit Asynchronous Binary Counter

14. Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter

15. The Binary State Sequence for a 3-bit Binary Counter CLOCK PULSE Q2Q2Q2Q2 Q1Q1Q1Q1 Q0Q0Q0Q0 Initially000 1001 2010 3011 4100 5101 6110 7111 8 (recycles) 000

16. A 4-bit asynchronous binary counter

17. The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

18. Exercise What do we mean by a modulus-n counter? What do we mean by a modulus-n counter? For both the modulus-16 and modulus-10 counters in the previous slide: For both the modulus-16 and modulus-10 counters in the previous slide: Redraw the schematic diagrams. Redraw the schematic diagrams. Sketch the timing diagrams. Sketch the timing diagrams. Sketch the truth tables. Sketch the truth tables.

19. Ripple Counter How does it work? How does it work? – When there is a positive Clock edge on the clock input of A, A complements. – The clock input for flip flop B is the complemented output of flip-flop A. – When flip-flop A changes from 1 to 0, there is a positive edge on the clock input of B causing B to complement.

20. Ripple Counter

22. The arrows show the cause-effect relationship. The corresponding sequence of states => (B,A) = (0,0),(0,1), (1,0), (1,1), (0,0), (0,1), … Each additional bit, C, D, …behaves like bit B, changing half as frequently as the bit before it. For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), …

23. Ripple Counter

24. Ripple Counter These circuits are called ripple counters because each edge sensitive transition (positive in the example) causes a change in the next flip-flop’s state. The changes “ripple” upward through the chain of flip-flops, i. e. each transition occurs after a clock-to-output delay from the stage before. To see this effect in detail look at the waveforms on the next slide.

25. “Ripple” Counter

26. Ripple Counter Starting with C = B = A = 1, equivalent to (C,B,A) = 7 base 10, the next clock increments the count to (C,B,A) = 0 base 10. In fine timing detail: – The clock to output delay tPHL causes an increasing delay from clock edge for A each stage transition. – Thus, the count “ripples” from least to most B significant bit. – For n bits, total worst case C delay is n tPHL.

27. Exercise Sketch a 4-bit Ripple Counter. Sketch a 4-bit Ripple Counter. This counter counts from ? to ? This counter counts from ? to ? Sketch the timing diagram for the: Sketch the timing diagram for the: Count-up sequence. Count-up sequence. Count-down sequence. Count-down sequence.

28. Synchronous Counters

29. SYNCHRONOUS COUNTERS All the flip-flops in the counter are clocked at the same time by a common clock pulse (external clock). All the flip-flops in the counter are clocked at the same time by a common clock pulse (external clock). 2 advantages compared to Asynchronous Counter : 2 advantages compared to Asynchronous Counter : 1) Very much less propagation delay time 1) Very much less propagation delay time 2) Able to perform counting sequence in random mode 2) Able to perform counting sequence in random mode (eg : 0,1,3,5,8, …,0,1,3,5,8,..) (eg : 0,1,3,5,8, …,0,1,3,5,8,..)

30. A 2-bit synchronous binary counter Assumed initial in binary 0 states meaning that both flip--flops are in RESET condition. Assumed initial in binary 0 states meaning that both flip--flops are in RESET condition.

31. Timing diagram for 2-bit synchronous counter

32. A 3-bit synchronous binary counter

33. Timing diagram for the counter

34. Synchronous Counter To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. For an up-counter, use an incrementer

35. Synchronous Counter

36. Internal Logic XOR complements each bit AND chain causes complement of a bit if all bits toward LSB from it equal 1 Count Enable Forces all outputs of AND chain to 0 to “hold” the state Carry Out Added as part of incrementer Connect to Count Enable of additional 4-bit counters to form larger counters

37. Synchronous Counter

38. The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

39. Timing example for a 74HC163.

40. The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)

41. Timing example for a 74LS160.

42. Other Counters – Down Counter - counts downward instead of upward – Up-Down Counter - counts up or down depending on value a control input such as Up/Down – Parallel Load Counter - Has parallel load of values available depending on control input such as Load Divide-by-n (Modulo n) Counter – Count is remainder of division by n which n may not be a power of 2 or – Count is arbitrary sequence of n states specifically designed state-by-state – Includes modulo 10 which is the BCD counter

43. Up/Down Counter

44. A basic 3-bit up/down synchronous counter

45. Up/Down Synchronous Counter Up Synchronous Counter : Up Synchronous Counter : UP is set to ‘1’ and AND gate 1 is active, causing output OR gate 1 to be HIGH. This will cause Q1 output to toggle. The AND gate 2 is also active, causing Q2 to toggle. UP is set to ‘1’ and AND gate 1 is active, causing output OR gate 1 to be HIGH. This will cause Q1 output to toggle. The AND gate 2 is also active, causing Q2 to toggle. Because of the JK connection from the Q output, the counting sequence is UP. Because of the JK connection from the Q output, the counting sequence is UP. Down Synchronous Counter : Down Synchronous Counter : DOWN is set to ‘1’ and AND gate 3 is active, causing output OR gate 1 to be HIGH. This will cause Q1 output to toggle. The AND gate 4 is also active, causing Q2 to toggle. DOWN is set to ‘1’ and AND gate 3 is active, causing output OR gate 1 to be HIGH. This will cause Q1 output to toggle. The AND gate 4 is also active, causing Q2 to toggle. Because of the JK connection from the Q output, the counting sequence is DOWN. Because of the JK connection from the Q output, the counting sequence is DOWN.

46. Timing Diagram Up/Down Synchronous Counter

47. The 74HC190 up/down synchronous decade counter.

48. Timing example for a 74HC190.

49. Parallel Load Counter

50. Counter with Parallel Load Add path for input data Add path for input data enabled for Load = 1 enabled for Load = 1 Add logic to : Add logic to : Disable count logic for Load = 1 Disable count logic for Load = 1 Disable feedback from outputs for Load = 1 Disable feedback from outputs for Load = 1 Enable count logic for Load = 0 & Count = 1 Enable count logic for Load = 0 & Count = 1

51. Counter with Parallel Load The resulting function table : The resulting function table : LoadCountAction 00 Hold Stored Value 01 Count Up Stored Value 1X Load D

53. Converting parallel load counter into sync. BCD counter Connect an external AND gate to LOAD Connect an external AND gate to LOAD Start with all-zero output (0000) Start with all-zero output (0000) COUNT input always HIGH (1) COUNT input always HIGH (1) BCD counts from 0000 to 1001 BCD counts from 0000 to 1001 To ensure LOAD = 1, Q0 and Q3 must be HIGH To ensure LOAD = 1, Q0 and Q3 must be HIGH LOAD input (D0  D3) = 0000 LOAD input (D0  D3) = 0000

54. Converting parallel load counter into sync. BCD counter

55. Synchronous BCD Counter Using D – type FF, list the present and next states in this Table. Present State Next State Q8Q4Q2Q1D8D4D2D1 0000 0001.......... 1001

57. Synchronous BCD Counter Y = 1, when present state = 1001 Y = 1, when present state = 1001 FF input equations FF input equations Obtained from next – state values Obtained from next – state values Simplify using K – map Simplify using K – map 1010  1111 (don’t care) 1010  1111 (don’t care) Y = Q1Q8 Y = Q1Q8

58. Modulo N Counter

59. Divide-by-n (Modulo n) Counter Count Count is the remainder of division by n which n may not be a power of 2, or Count is arbitrary sequence of n states specifically designed state-by-state Includes modulo 10 which is the BCD counter

60. Counting Modulo N A counter that goes through a repeated sequence of N states. A counter that goes through a repeated sequence of N states. Maximum decimal number to be counted : Maximum decimal number to be counted : If Mod 16, then the max decimal number is 15 If Mod 16, then the max decimal number is 15 If Mod N = 2 n then the max decimal counted is N-1 If Mod N = 2 n then the max decimal counted is N-1 To determine the required number of flip-flops: To determine the required number of flip-flops: n flip-flop 2 n output = Mod N n flip-flop 2 n output = Mod N

61. Counting Modulo 7 Use a synchronous 4 – bit binary counter with a synchronous load and clear Use a synchronous 4 – bit binary counter with a synchronous load and clear LOAD – detect count “6” and load “0” LOAD – detect count “6” and load “0” Gives count of ( 0,1,2,3,4,5,6,0,1….) Gives count of ( 0,1,2,3,4,5,6,0,1….) Using don’t care for states above 0110, detect number “6” when LOAD = Q2.Q1 Using don’t care for states above 0110, detect number “6” when LOAD = Q2.Q1

62. Counting Modulo 7

63. A synchronous 4-bit binary counter with a synchronous load and an asynchronous clear is used to make a Modulo 7 counter Use the Load feature to detect the count "6" and load in "zero". This gives a count of 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 0,... Using don’t cares for states above 0110, detection of 6 can be done with Load = Q4 Q2 Counting Modulo 7: Synchronously Load on Terminal Count of 6 D3 Q3 D2 Q2 D1 Q1 D0 Q0 CLEAR CP LOAD Clock 0 0 0 0 Reset

64. Counting Modulo 6 : special requirement Requirement : synchronously preset “9” on RESET and LOAD “9” on terminal count “14” Requirement : synchronously preset “9” on RESET and LOAD “9” on terminal count “14” Use a synchronous, 4 – bit counter with a synchronous LOAD Use a synchronous, 4 – bit counter with a synchronous LOAD Use LOAD signal to : Use LOAD signal to : preset count to “9” preset count to “9” detect count “14” detect count “14” Give count of (9,10,11,12,13,14,9,10,…) Give count of (9,10,11,12,13,14,9,10,…)

65. Counting Modulo 6 : special requirement

66. A synchronous, 4-bit binary counter with a synchronous Load is to be used to make a Modulo 6 counter. Use the Load feature to preset the count to 9 on Reset and detection of count 14. This gives a count of 9, 10, 11, 12, 13, 14, 9, 10, 11, 12, 13, 14, 9, … If the terminal count is 15 detection is usually built in as Carry Out (CO) Clock D3 Q3 D2 Q2 D1 Q1 D0 Q0 CLEAR CP LOAD 0 0 1 1 Counting Modulo 6: Synchronously Preset 9 on Reset and Load 9 on Terminal Count 14 Reset 1

67. Arbitrary Count Sequence Design a counter with six states as in table below Design a counter with six states as in table below

68. State Diagram Figure 7-16 (b)

69. Arbitrary Count Sequence 2 states are not included : 011 and 111 (don’t care conditions). 2 states are not included : 011 and 111 (don’t care conditions). Simplified equations : Simplified equations :

70. Arbitrary Count Sequence Logic diagram of the counter Logic diagram of the counter

71. Cascaded Counters

72. CASCADED COUNTERS Two cascaded counters (all J and K inputs are HIGH).

73. A modulus-100 counter using two cascaded decade counters.

74. Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.

75. Example: Determine the overall modulus of the two cascaded counter for (a) and (b) For (a) the overall modulus for the 3 counter configuration is 8 x 12 x 16 = 1536 for (b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x 5 = 1400

76. A divide-by-100 counter using two 74LS160 decade counters.

77. A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D 0 is the LSB in each counter).

78. Counter Decoding

79. Decoding of state 6 (110). COUNTER DECODING * To determine when the counter is in a certain states in its sequence by using decoders or logic gates.

80. A 3-bit counter with active-HIGH decoding of count 2 and count 7.

81. A basic decade (BCD) counter and decoder.

82. Outputs with glitches from the previous decoder. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

83. The basic decade counter and decoder with strobing to eliminate glitches.

84. Strobed decoder outputs for the circuit

85. Counter Applications

86. Simplified logic diagram for a 12-hour digital clock.

87. Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

88. Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

89. Functional block diagram for parking garage control.

90. Logic diagram for modulus-100 up/down counter for automobile parking control.

91. Parallel-to-serial data conversion logic.

92. Example of parallel-to-serial conversion timing for the previous circuit

93. Assignment Folder Contents 10:-3, -4, -5, -6, -7, -8, -9, 10:-3, -4, -5, -6, -7, -8, -9, -10, -14, - 15, -16, -17, -18, -19 -10, -14, - 15, -16, -17, -18, -19

94. Thank You.