1. Commissioning Experience and Status Burkard Reisert (FNAL) L2 installation readiness review:

2. SLINK Pulsar pre-processors L1 Muon L1 Tracks L1 Trigger decsion Trigger Supervisor L2 CALO (Cluster/ IsoCluster) Energy Sums Shower Max SVT Muon Cluster Electron Merger SVT L2toTS Level 2 Upgrade System configuration Merger Phase I: single PC configuration Phase II: dedicated PC for each L2 buffer Strategy: Commission parasitically  need to split all input signals (fiber + LVDS) SLINK-PCI PC Linux PCs: decision PC control

3. Pulsar Board mezzanine card Connectors (optical fiber interfaces) connectors for all LVDS interfaces of legacy input systems (Rx & Tx) VME interface Slink interface FPGA Data merging & control FPGAs DataIO L1 decision & Tracks visible to all 3 FPGAs

4. Pulsar MOAB (Mother of All Boards) Design& Verifications: ~ 3 people in ~ 9 months Result: No blue wire on all prototypes All prototypes became production boards Custom mezzanine cards types: 2 Rx for L2 System 2 Tx for test stand Initial checkout ALL interfaces: ~ 2 people in ~ 1 month works up to 100 MHz AUX Card CERN SLink HOTLINK TAXI

5. Hardware counts Pulsar boards: 59 10 Level2 systems ( 1 (Run IIa) + 9 (Run IIb)) 22 for SVT RW (15), SVT upgrade dev (5), XFT upgrade (2) Hotlink Rx: 17 fiber + 5 Hotlink+lvds 4+5 (Run IIa + IIb) + 1lvds (Run IIb) Hotlink Tx: 17 fiber + 5 Hotlink+lvds Taxi Rx: 42 14 (Run IIb) Taxi Tx: 22 AUX Card: 3.3V: 20, 5V: 5 8 (Run IIb) Slink LDC/LSC Hola: 19 pairs 9 pairs (Run IIb) Slink S32PCI64: 6 3 (Run IIb) Note: Apply factor 1-1.5 to run IIb needs to avoid hardware shortage for development & commissioning

6. Testing Hardware testing board checkout with standalone VME code Firmware testing run control driven Tx  Rx (slink formatter)  Slink Rx - calib continuous, normal mode/myron mode,L2 Auto/L1 Alt rates ~< 2kHz - test stand sparky setup random trigger sequence dial L1 and L2 accept rate upto 30kHz L1 Cosmic and L2 torture Parasitic beam tests Dedicated beam tests

7. Test Stand for Production Testing TS L1 Mezz. Using: dedicated Test firmware standalone c-code Tested features: VME access Internal RAM and SRAM Internal communication TS interface SVT/XTRP L1 Signals Mezzanine card Interface Slink Interface Documented by Angie Little AUX Tx Rx Mezz. SVT/XTRP SLINK

8. Muon Rx Firmware Inputs: hotlink fibers muon matchbox & prematch box L1 Trigger bits XTRP cable Select data that is actually used in L2 decisions Zero suppress muon data Slink formatter: 1 package Containing L1 bits, Track data, zero suppressed Muon data Diagnostic DAQ Buffers Muon inputs on DataIO FPGAs XTRP input and Slink output on Control FPGA ~ 1 month of parasitic running, no problems found (low level bit errors (1 in >100,000) proven to be upstream)

9. SVT Rx Firmware Inputs: SVT cable (VTM from SRC) Select data that is actually used in L2 decisions (ala TL2D) Slink formatter: 1 package SVT data Diagnostic DAQ Buffers SVT Input and Output on Control FPGA Timing of input data for Current and previous event, begin and end of package ~ 1 month of parasitic running, no problems found

10. Reces Rx Firmware (3 boards) Inputs: 16 TAXI fibers implemented algorithm: pass on all data (will change to zero suppression to meet latency goal: non SVT data < SVT data in all events) Slink formatter: 1 package RECES data Diagnostic DAQ Buffers Fiber Inputs on DataIO FPGAs Slink output on Control FPGA ~ 3 weeks of parasitic running, see Chris talk for known features Note: Control FPGA Identical to Slink merger

11. Slink Merger Inputs: Up to 4 Slink inputs (HOLA LDC) Algorithm: Merge up to 4 inputs, which are enabled through register Record all inputs Slink formatter: 1 output Slink package Diagnostic DAQ Buffers Slink Inputs on DataIO FPGAs Slink output on Control FPGA ~ 2 weeks of parasitic running (core firmware), no errors found Note: Timing of input data for Current and previous event, begin and end of package ( last store)

12. Inputs: 1 Slink LDS (from CPU) TS Interface cable Algorithm: Record return message from CPU Handshake with TS Note: Global timing info L1A  L2A/R Start and end of TS handshake Diagnostic DAQ Buffers CPU return on DataIO FPGA(s) Global timing on Control FPGA ~ 3 weeks of parasitic running (core firmware), no errors found Note: Timing of input data for Current and previous event, begin and end of package ( last store) Level2 to Trigger supervisor

13. DAQ readout (TP2D bank) Each pulsar board (Muon/SVT/RECES/Cluster/Merger/L2toTS) provides a lot of diagnostic information. use a very flexible readout configuration to keep readout times low Only readout selected boards enable/disable single DAQ buffers fixed length or variable length readout board level readout list Readout configured through Hardware database parameters

14. New parameters Dial number of words per DAQ RAM Board level Readout list Deal with remapped Fiber Input DAQ Solution: more flexible Readout Configurartion: C1C1 C2C2 D1 1 D1 2 D2 1 D2 2 Muon var 256---256--- Reces 21---16---16--- SVT var (var)---------- Cluster var---8*64var8*64var Merger var---var (var) L2toTS 13var2--- Thanks to Bill & Jane

15. Taxi Tx Hotlink Tx Taxi Rx Hotlink Rx splitters Power meter Fiber Splitter Lab Muon Tracks L2 Muons Legacy Level 2 Decision Crate  - Processor 1/3 RECES Reces Cluster SVT CList ISOList SVT Optical LVDS Splitters A Parallel Universe for the Pulsar LVDS Fanout board

16. Muon SVT L2toTS Trigger Supervisor PULSAR Configuration for Initial Beam Test L1 muon L1 track L1 bits SVT Control node - monitor info - interact with RC Goal: Demonstrate the full chain Input Data  Pulsar Receiver  Slink/PCI  CPU  PCI/Slink  L2toTS CPU running some simple algorithms based on L1/Muon/XTRP/SVT Test runs: Pulsar and Alpha driving the system with same trigger table Smooth Operation w/o Silicon and w/ Silicon L=20E30; L1A 14kHz L2A~60Hz Linux PC

17. SLINK Muon Electron Merger SVT L2toTS ShowMax (Reces) 1/3 Data 2/3 Tx SLINK Trigger Supervisor L1 muon L1 track L1 bits SVT Cluster SlinkTx RecesTx Goal: Experience in realistic environment Test complete Pulsar L2 System Test runs: Pulsar and Legacy L2 (Alpha) driving the system Smooth Operation L=60E30; L1A 21kHz, L2A~100Hz PULSAR System Configuration in Beam Tests realistic test pattern SLINK Linux PC

18. Test data taking with a subset of Triggers (using Muon, Track and displaced Vertex) 1) Legacy L2 making the decision Pulsar system running parasitically 2) Pulsar making the decision Perfect match of trigger decisions Of both systems before and after prescales Beam Tests August 2004

19. SLINK Pulsar pre-processors L1 Muon L1 Tracks L1 Trigger decsion Trigger Supervisor L2 CALO (Cluster/ IsoCluster) Energy Sums Shower Max SVT Muon Cluster Electron Merger SVT L2toTS PULSAR System Timing Measurements Merger SLINK-PCI Linux PC SVT input Handshake with TSI & L1A  L2A/R buffer specific counters on L1A - current event - previous event (unbiased) Decision Merger inputs

20. New system (not optimized) already as fast as CDF Legacy Level2 Timing measurements give guideline for optimization. Goal: latency nonSVT<SVT System timing measurements L2 Legacy Silicon Vertex Trigger Tail due to Silicon Vertex Trigger processing time ss ss Alpha Pulsar (on first shot) CPU: Xenon CPU: AMD will be faster Overall L1A to L2 Decision latency

21. Decision returned, Handshake TS, Global L2A/R (previous event) -- Decision returned -- TS handshake starts -- TS handshake ends -- Global L2 Decision (broadcasted on back plane)  t = 0.8  s (will be reduced)  t = 0.6  s  t = 1.7  s

22. ss ss ss System timing measurements Muon/Tracks/L1 Shower Max (Electron) Silicon Vertex Trigger Provide very valuable guide line for system optimization: e.g. - SVT on separate Slink to PCI path - select subsystem path to optimize first (Muon/Tracks/L1 vs. ShowerMax)

23. Reces Merger ShowMax (Reces) SLINK “final” Merger SLINK Reces Rx Reces Data arriving at Reces Rx:Reces Data arriving at Merger 8  s 15  s L1A Room for improvements: -- reduce overhead in RecesRx state machines -- zero suppress Reces Data -- optimize Merger Total reduction of Reces Path latency > 3  s Latencies in Reces Data Path

24. Hardware is in good shape Firmware is in reasonable shape, needs fine tuning/testing in some cases Commissioning an impressive amount of results has been achieved we were very productive as a team, we need to keep the momentum going to meet the goal: “commissioning in March 2005” Summary

25. Backup

26. One picture worth a thousand words:LEVEL2_PULSAR_00 crate MUONMUON RECESRECES RECESRECES RECESRECES SVTSVT CLUCLU L2toTSL2toTS MERGERMERGER MERGERMERGER

27. Physics table PULSAR_TEST_v-1 1.Physics Table PULSAR_TEST_v-1 1.Dataset DECOUPLED_DEFAULT_v-1 INCLUSIVE/StreamI 1.Path L2_INCLUSIVE_ALL_v-1 1.Trigger L2_INCLUSIVE_ALL_2HZ_v-1 Bit: [3] 2.Path MB_XING_PS1M_v-2 1.Trigger L1_MB_XING_PS1M_v-2 Bit: [23] 2.Trigger L2_AUTO_L1_MB_XING_v-2 Bit: [0] 2.Dataset TEST_PULSAR_v-1 null/StreamI 1.Path L1_SEVEN_TRK2_PS0_DECOUPLED_v-1 1.Trigger L1_SEVEN_TRK2_PS0_v-1 Bit: [0] 2.Trigger L2_AUTO_L1_SEVEN_TRK2_v-1 Bit: [1] 2.Path L2_B_CHARM_LOWPT_v-1 1.Trigger L1_TWO_TRK2_DPHI90_PS1_v-1 Bit: [1(3)] 2.Trigger L2_B_CHARM_LOWPT_L1_DPS_v-3 Bit: [2] 3.Path L2_PS10_L1_MB_CLC_PS10K_v-1 1.Trigger L1_MB_CLC_PS10K_v-2 Bit: [21] 2.Trigger L2_PS10_L1_MB_CLC_v-1 Bit: [4] 4.Path L2_PS10_L1_TWO_CMU_1.5_PT1.5_v-1 1.Trigger L1_TWO_CMU1.5_PT1.5_v-4 Bit: [2(2)] 2.Trigger L2_PS10_L1_TWO_CMU1.5_PT1.5_v-1 Bit: [5] 5.Path L2_PS1K_L1_TWO_TRK2_DPHI90_v-1 1.Trigger L1_TWO_TRK2_DPHI90_PS1_v-1 Bit: [1(3)] 2.Trigger L2_PS1K_L1_TWO_TRK2_DPHI90_v-1 Bit: [6] 6.Path L2_TWO_CMU1.5_PT1.5_DPHI120_OPPQ_v-1 1.Trigger L1_TWO_CMU1.5_PT1.5_v-4 Bit: [2(2)] 2.Trigger L2_TWO_CMU1.5_PT2_DPHI120_OPPQ_v-1 Bit: [7] 7.Path L2_TWO_TRK8_L1_TWO_TRK2_DPHI90_v-1 1.Trigger L1_TWO_TRK2_DPHI90_PS1_v-1 Bit: [1(3)] 2.Trigger L2_TWO_TRK8_PS100_v-1 Bit: [8] Special Trigger table based on L1/Muon/XTRP & SVT inputs Pulsar and Alpha Decision agree Identical rates More details on the trigger table