1. CSI-2111 Computer Architecture Ipage 9-1 9. Control, memory and I/O v Objectives: –To define and understand the control units and the generation of sequences. –To know the various types of memory. –To understand and use the RAM –To know the ways of reaching the peripherals of inputs/outputs.

2. CSI-2111 Computer Architecture Ipage 9-2 Organization of the computer... Last stage!!! ROM (Combinational) RAM (Sequential) Registers (Sequential) Decoders (Combinational) Adders (Combinational Others... (Combinational) ALUCounters (Sequential) CPUInputs / Outputs Computer

3. CSI-2111 Computer Architecture Ipage 9-3 9.1 Storage unit Memory 2 k registers with N bits each one D e c o d e r Memory address register k bits (MAR) Register of information n bits (MDR) Read/ write Data Address

4. CSI-2111 Computer Architecture Ipage 9-4 Block Diagram Storage unit 2 k registers N bits word Read K lines of address Write N lines of output data n lines of data input

5. CSI-2111 Computer Architecture Ipage 9-5 RAM (Random Access Memory) v Random access storage, allowing reading and writing of information. It is often called read-write memory. The contents are destroyed in absence of power. v 2 types: –SRAM ( Static RAM ) –DRAM ( Dynamic RAM )

6. CSI-2111 Computer Architecture Ipage 9-6 Types of RAM v In addition to the SRAM and DRAM, we find: –EDORAM (Extended dated out RAM) and Burst-mode RAM for sequential access to the data –Flash memory and FRAM (Ferroelectric RAM) for nonvolatile memory –VRAM (Video RAM), WRAM (Window RAM), 3d RAM for the video memory –SDRAM (Synchronous DRAM) –Memory with local hiding place: CDRAM (Cached DRAM), EDRAM (Enhanced DRAM), CVRAM (Cached VRAM) –MEMORY GDR RAM

7. CSI-2111 Computer Architecture Ipage 9-7 ALU MAR MDR PC OpCodeOpAddrA HZN Control M A I N M E M O R Y DSRW 9.2 Control unit

8. CSI-2111 Computer Architecture Ipage 9-8 A) Word Time for serial operation mode v Type of sequence necessary for the serial transfer between two registers. The produced signal corresponds to the transfer time of a word v # bits = # of required clock ticks. C Start Stop Q Time of a word (8 bits) 12345670

9. CSI-2111 Computer Architecture Ipage 9-9 A) Word Time for serial operation mode v Realization using a SR flip-flop and a binary counter. S R C Q C 3 bits counter (with enable ) C Start Stop Count enable Control signal

10. CSI-2111 Computer Architecture Ipage 9-10 A) Word Time for serial operation mode v Quiz : What should be modified in the preceding diagram for a word length of: –a) 5 clock pulses –b) 13 clock pulses v Think about the counter and about the inputs of the AND gate...

11. CSI-2111 Computer Architecture Ipage 9-11 a) 5 ticks v Realization using a SR flip-flop and a binary counter of modulo 5. S R C Q C 3 bits counter (modulo 5) C Start Stop Count enable Control Signal 2

12. CSI-2111 Computer Architecture Ipage 9-12 b) 13 ticks v Realization using a SR flip-flop and a binary counter of modulo 13. S R C Q C 4 bits Counter (modulo 13) C Start Stop Count enable Control Signal 2323 2

13. CSI-2111 Computer Architecture Ipage 9-13 B) Word Time for parallel operation mode C T0T0 T1T1 T2T2 T3T3 We see 2 different implementations.

14. CSI-2111 Computer Architecture Ipage 9-14 B) Word Time for parallel operation mode v a) Realization with counter and decoder T 0 T 1 T 2 T 3 Decoder 2 x 4 2 bits Counter

15. CSI-2111 Computer Architecture Ipage 9-15 B) Word Time for parallel operation mode v b) Realization with circular counter (ring counter) composed of a circular shift register where, at any time, only one flip-flop has the logical value "1". This value is shifted with each clock pulse. Initially, the counter contains 1000. T 0 T 1 T 2 T 3

16. CSI-2111 Computer Architecture Ipage 9-16 Self-correcting counters v The use of a counter can also lead to problems that certain states are unutilized. It is then necessary it to make it self-correcting, to tolerate such case. Example: sequence of counting 0, 1, 2 00011011 ?

17. CSI-2111 Computer Architecture Ipage 9-17 Self-correcting counters v Not self-correcting. If the counter falls, by error, in an invalid state 3, it will remain there indefinitely (or until a forthcoming error). 00011011

18. CSI-2111 Computer Architecture Ipage 9-18 Self-correcting counters v Self-correcting! The invalid state 3 leads (directly or indirectly) to a valid state in the counting sequence 00011011

19. CSI-2111 Computer Architecture Ipage 9-19 Self-correcting counters v One can make the counters self-correcting at the time of their design (for example, one decides that state 3 will have 0 like following state). That can make the circuit more complex (there is less of X in the Karnaugh map). v If one leaves the following state of 3 unspecified (X) at the time of the design, that does not necessarily say that the circuit will not be self-correcting. It may be the case that the groupings of X make that state 3 a valid state (0, 1 or 2).

20. CSI-2111 Computer Architecture Ipage 9-20 9.3 Bus and circuits of I/O v Inputs/outputs Module –Transfer of data between the memory and the I/O circuits (connected to the peripherals), with or without the CPU intervention. –Interface, controller and I/O processor –Modes of transfer, DMA v Interrupts

21. CSI-2111 Computer Architecture Ipage 9-21 Inputs/outputs Module (I) v Bus for control, addresses, data comm., and the I/O operations. v Part of the memory addresses is used to address ports connected to the I/O circuit. v There are no instructions for distinct I/O (load/store and read/write with the I/O). CPU I/O Circuit Shared memory I/O

22. CSI-2111 Computer Architecture Ipage 9-22 Inputs/outputs Module (II) v Bus for address and data comm., but control bus for the memory access is different from I/O operation. v The memory addresses and the ports connected to the I/O circuit are independent v There are distinct instructions for reading and writing with the I/O. CPU I/O Circuit Independent memory I/O

23. CSI-2111 Computer Architecture Ipage 9-23 Inputs/outputs Module (III) v Two sets of different bus (control, addresses, data), one for the memory access and the other for the I/O operations. v The memory addresses and the ports connected to the I/O circuits are independent v There are distinct instructions for reading and writing with the I/O. CPU, DMA controller or I/O processor I/O CircuitDMA Memory

24. CSI-2111 Computer Architecture Ipage 9-24 Complementary readings v Mano and Kime: –6.2-6.4 : RAM (except Waveforms Timing) –7.5, 7.6, 7.9-7.11 : Bus and Data –8.1-8.4, & 8.8 : Control unit –11.1, 11.3, 11.5, 11.7 : I/O and DMA