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Published bySilas Butler Modified over 8 years ago
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Why we need adjustable delay? The v1495 mezzanine card (A395A) have a signal transmission time about 6ns. But we need all the signals go into the look up table at the same time. 6ns delay
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How to solve it? Signal going to the A,B port Signal going to the D,E port A,B D,E 1 A,B D,E 2 A,B D,E 3 6ns
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Input flip-flop 371MHz (now 350) signal D flip-flop signal Mode 7 counter Decoder Multiplexer data D flip-flop w/ enable 12-16 Decoder 96-128 Multiplexer 96-128 DFFE
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DFF1 Last page DFF2 LV1 LUT LV3 LUT LV2 LUT LV4 LUT LV5 LUT DFF Output Flip- flop 53MHz
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Some Estimate The delay from input to output is about (9x18.86=169.74)+?? ns. The worst case, each channel from input to LUT part cost about 25 logic elements. Memory space only need 2048 bits.
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