1. Computer Architecture Lecture 4 Sequential Circuits Ralph Grishman September 2015 NYU

2. Time and Frequency time = 1 / frequency frequency = 1 / time units of time millisecond = 10 -3 second microsecond = 10 -6 second nanosecond = 10 -9 second picosecond = 10 -12 second units of frequency kiloHertz (kHz) = 10 3 cycles / second megaHertz (MHz) = 10 6 cycles / second gigaHertz (GHz) = 10 9 cycles / second 9/16/15Computer Architecture lecture 42

3. Today’s Problem A typical clock frequency for current PCs is 2 GHz. For the original IBM PC’s, it was 4.77 MHz. About how many times faster is the clock on a current PC? (a) 2.385 (b) 42 (c) 400 (d) 4000 9/16/15Computer Architecture lecture 43

4. Solution New Frequency = 2 GHz = 2 * 10 9 Hz Old Frequency = 4.77 MHz ≈ 5 MHz = 5 * 10 6 Hz Ratio = 2 * 10 9 / 5 * 10 6 = 400 9/16/15Computer Architecture lecture 44

5. Combinational vs. sequential circuits in a combinational circuit, output (after some delay) is a function of inputs in contrast, a sequential circuit holds state information: – the output is a function of the state of the device, as well as its inputs – in other words, sequential circuits have memory 9/16/15Computer Architecture lecture 45

6. A very simple 2-state circuit 9/16/15Computer Architecture lecture 46

7. A very simple 2-state circuit 1 state 9/16/15Computer Architecture lecture 47 0 1

8. A very simple 2-state circuit 0 state 9/16/15Computer Architecture lecture 48 1 0

9. What’s the problem? 9/16/15Computer Architecture lecture 49

10. We cannot change the state 9/16/15Computer Architecture lecture 410

11. RS Latch Solution: change from inverters to NOR gates: when R = S = 0, has two stable states (Q = 0 or Q = 1) 9/16/15Computer Architecture lecture 411 Q R S

12. RS Latch set: changing S to 1 forces Q=1; when S is returned to 0, Q=1 state is retained reset: changing R to 1 forces Q=0; when R is returned to 0, Q=0 state is retained 9/16/15Computer Architecture lecture 412 Q R S

13. D latch when C [clock] input is 0, latch retains current state setting C to 1 forces Q=D ["load data"]; when C is returned to 0, state is retained 9/16/15Computer Architecture lecture 413

14. D latch timing 9/16/15Computer Architecture lecture 414

15. Register A register is a set of latches with a common clock 9/16/15Computer Architecture lecture 415

16. Synchronous Circuit a set of registers controlled by a common clock + a combinatorial circuit to compute the next state 9/16/15Computer Architecture lecture 416 next state next state register C

17. Synchronous Circuit: Up Counter 9/16/15Computer Architecture lecture 417 +1 register C

18. Problem: counter doesn’t work Reason: race condition Solution: edge-triggered flip-flop for register loads data only on falling edge of clock 9/16/15Computer Architecture lecture 418

19. Master-slave flip-flop Loads data only on falling edge of clock 9/16/15Computer Architecture lecture 419

20. D flip-flop timing edge-triggered MS FF 9/16/15Computer Architecture lecture 420

21. How fast? How fast can we clock a synchronous circuit? Clock period > delay of combinatorial circuit + setup and delay times of register 9/16/15Computer Architecture lecture 421

22. Register File Holds all (programmable) processor registers At a minimum, must provide data input (for register write) data output (for register read) register number write signal 9/16/15Computer Architecture lecture 422

23. Register File A typical instruction will read two registers, do some calculation, and store the result in a third register We can do this faster if in the same clock cycle we can read both operand registers write the result register we do this through multiple register ports 9/16/15Computer Architecture lecture 423

24. Register File 9/16/15Computer Architecture lecture 424

25. Read Port 9/16/15Computer Architecture lecture 425

26. Write Port 9/16/15Computer Architecture lecture 426

27. A Decoder 9/16/15Computer Architecture lecture 427