1. FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Spring 2007 Instructor: Dr. Michael Frank Module #13: Latches and Flip-Flops (Thanks to Dr. Perry for some slides)

2. FAMU-FSU College of Engineering Topics covered in this Module  Topic 3. Sequential Digital Logic Subtopic 3.1. Basic Sequential Elements: Latches & Flip-Flops.  3.2.1. Basic (SR, D, JK) latch/FF implementations using logic gates  3.2.2. Implementations using CMOS transmission gates. CIO 7. [LatchFF] Analyze characteristic tables and timing diagram of D latches and D flip-flops.

3. FAMU-FSU College of Engineering Outline of Lecture  Fundamental concepts of sequential logic: Storing bits of state info. using bistable elements Latches versus flip-flops Sequential updating of state information  Finite State Machine models  Simple latch designs Switch-based, transmission-gate based, logic-gate based  Distinction between static vs. dynamic latches SR latches and D latches  Simple flip-flop designs Transmission-gate based, logic-gate based D flip-flops and JK flip-flops

4. FAMU-FSU College of Engineering Combinational vs. Sequential Logic  Combinational logic circuits: Contain no feedback loops  Circuit outputs never “wrap back around” to feed circuit inputs Have no persistent memory  As soon as new inputs are received, new outputs are computed directly from them, and the old outputs are forgotten. Require an amount of hardware that is proportional to the number of operations that must be performed in an algorithm.  A given piece of hardware cannot be reused several times during the processing of the same piece of input data. Are usually self-timed  Data is allowed to propagate through the circuit as fast as it can, with no external control  Sequential logic circuits: Contain feedback loops Can have persistent memory  Internal bits of state that are not all necessarily subject to change as soon as new inputs are received. Can execute iterative algorithms with low hardware cost, via sequential reuse  Steps of the algorithm may be carried out by reusing the same piece of logic hardware over and over again Are usually regulated by a clock  This controls the timing of the sequence of steps of the algorithm being carried out  This minimizes the effects of propagation delay variations

5. FAMU-FSU College of Engineering The Ring Oscillator: The Simplest Sequential Logic Circuit  Consider connecting three inverters to each other in a loop, like this: What will this circuit do?  Go around and around, constantly flipping its bits, in an infinite loop  Some problems with this circuit: There are no inputs  Output has limited usefulness Its precise behavior and timing are uncontrolled 1 0 1 0 1 0 In this lecture, we’ll be exploring design method- ologies for build- ing more useful, well-controlled sequential circuits.

6. FAMU-FSU College of Engineering Bistable Elements  To store (remember) a bit of information, you need a bistable element a physical system that has (at least) two naturally stable states  I.e., a very slow background rate of spontaneous transitions between states  Some familiar examples: Toggle switch, coin on a table  Of course, we can also build bistable elements electronically! Charge stored on an isolated capacitor State of a logic circuit with feedback

7. FAMU-FSU College of Engineering Concept for a Simple Capacitor-Based Storage Element  Connect one terminal of the capacitor to a single-pole, double-throw switch, which can connect to V dd (logic high voltage), GND (logic low voltage), or to neither. Connect to V dd  Store a 1 Connect to GND  Store a 0 Disconnect   Capacitor holds stored value, for a time (it gradually decays) GND V dd Since the stored charge changes dynamically (on its own) over time, this is called dynamic storage. This method of infor- mation storage is the basis of DRAM (dynamic random- access memory).

8. FAMU-FSU College of Engineering Implementing the Capacitive Storage Concept using Transistors (DRAM cell)  Replace the SPDT switch with: An externally-controlled data input port in Externally-controlled complementary pair of signals p, ~p controlling a transmission gate  When “pass” signal p=1 (~p=0), transmission gate is on (conducting) out = M = in  When p=0 (~p=1), transmission gate is off (nonconducting) out = M = const.  Value is held capacitively. C should be substantial  In an actual DRAM cell, the transmission gate is usually replaced by a single nFET transistor. This is the simplest possible “D latch” (data latch) inout p ~p M in out M 2 p,~p C C Dynamic D latch Transmission gate

9. FAMU-FSU College of Engineering What is a Latch? My Data  A latch is a bistable storage element that has (at least) two operating modes: An unlatched or transparent mode, in which changes to certain inputs are immediately reflected at the output.  An unlatched latch allows data to pass through it unimpeded Like an unlatched latch on a baby gate allows toddlers to pass through unimpeded A latched or held mode, in which the output remains stable (at the stored value) regardless of what is happening to the latch inputs.  The information is “latched in place” and is remembered, as long as we are in this mode

10. FAMU-FSU College of Engineering A Basic Static Bistable Element – Cross-Coupled Inverters  Clearly, the logic circuit at right has two stable states… It can thus serve as a bistable storage element.  It is called a “static” storage element, because the voltage levels will remain stable indefinitely,  as long as power is supplied to the inverters.  Only question: How do we change its state? 1 10 0

11. FAMU-FSU College of Engineering A Simple Static D Latch Using Inverters and Transmission Gates  When p=1, the input in directly connects to the storage node M Just like in the DRAM case.  When p=0, the input is disconnected, and M is instead driven by the bottom inverter And is thus maintained at the same value, ~~M = M. in p,~p ~p,p out M ~M Compare to the dynamic D latch of a few slides back # of transistors: 8 (2 in ea. inverter & ea. T-gate)

12. FAMU-FSU College of Engineering Characteristic Table of D Latch pin out (q t ) 100 111 0dq t−1 pin out (q t ) 1xx 0dq t−1 abbreviated version transparent latched output is the same as a moment before

13. FAMU-FSU College of Engineering Set-Reset (SR) Latch Using NAND Gates  Replace inverters in the previous example with NAND gates Use extra inputs of gates, instead of T-gates, to control the latch.  If ~S (set) and ~R (reset) are never both asserted, When ~R is asserted (0), ~M = 1, and so M=0  out. When ~S is asserted (0), M = 1  out, and ~M = 0. When neither is asserted (both are 1), the NANDs become equivalent to NOTs, and the circuit holds its state like cross-coupled inverters. out ~R ~S M ~M M ~R ~S out the same circuit drawn in two different ways

14. FAMU-FSU College of Engineering Characteristic Table of SR Latch ~S~R out (q t ) 011 100 11q t−1 00error “set” (to 1) asserted “reset” (to 0) asserted latched not latched Output is 1 in this particular circuit, but will be undefined after ~S and ~R get deasserted. Because of this, this input case is “illegal” (disallowed).

15. FAMU-FSU College of Engineering Building a D latch from an SR latch  Incorrect attempt #1: Since R=0 causes out=0, let’s rename ~R to D (data in), and generate ~S from the complement of D, so that when D=1, we’ll get out=1. Can you see the problem with this design? It passes data through OK… But, this “latch” is always unlatched!  It’s logically equivalent to a wire that connects D directly to out.  How do we fix this problem? (See next slide.) M ~M D out ~R ~S Clue: There is no input to control the latch mode!

16. FAMU-FSU College of Engineering Completed D-latch Design  To turn that fancy wire back into a latch, we need to add a “latched” mode, in which both ~S and ~R are deasserted (1). Generate ~S and ~R with two NAND gates, which will output 1 whenever the ~L “latch” input is asserted (0). When ~L = 1 (deasserted), these NANDs act like NOTs, and copy D and its complement over to ~R and ~S, resp. M ~M D out ~R ~S ~L ~D

17. FAMU-FSU College of Engineering Characteristic Table of This D Latch ~LD out (q t ) 1xx 0dq t−1 transparent latched Same as the previous D latch example, just using different symbols for the inputs.

18. FAMU-FSU College of Engineering Sequential Logic with Latches  Given just latches, we can directly implement any desired sequential algorithm as follows: When a “clock” signal goes high, the upper bank of latches goes transparent  And the right-hand combinational logic receives new inputs and computes new outputs. Then, when the clock goes low, the upper latches latch, and the lower bank of latches goes transparent.  Then the left-hand combinational logic receives new inputs and computes new outputs The process repeats each clock cycle, and the data can be transformed iteratively over many sequential steps. ~L clock comb. logic Possible hazard (race condition): Both sets of latches may briefly be transparent, just after a rising edge… “Fast” signals through combinational logic may circulate all the way around & corrupt state

19. FAMU-FSU College of Engineering Next Topic: Flip-Flops  A flip-flop is similar to a latch, except that: Its state is only “unlatched” (subject to change) for very brief periods  Usually, during a rising or falling edge of some controlling clock signal Depending on the particular flip-flop design, the new output may depend on what the controlling input was at a considerably earlier time  I.e., the flip-flop may have some significant built-in internal delay (typically, ½ a clock cycle) between input sampling and output modification

20. FAMU-FSU College of Engineering Common Types of Flip-Flops  SR (set-reset) flip-flop: Controlled by R and S inputs, like an RS latch  But, state changes are edge-triggered instead of level-enabled.  JK flip-flop: Has inputs named J and K, similar to S and R… Behavior is very similar to an SR flip-flop  Except that when both J and K are asserted, the flip-flop toggles its state (new state  NOT old state) on the active clock edge.  T (toggle) flip-flop Like a JK flip-flop, but lacks separate J and K inputs.  Is always toggled on the active edge, or if an optional T input is asserted.  D (data) flip-flop Controlled by a D (data) input, like a D latch  But, state changes are edge-triggered instead of level-enabled

21. FAMU-FSU College of Engineering More slides to come…  Show internal structure of various flip-flops…

22. FAMU-FSU College of Engineering Dr. Perry’s Slides Following are some old slides by Dr. Perry on Latches & Flip-Flops, left over from previous semesters…

23. Memory Devices

24.  Data Latch (D-latch)  Flip-flops (edge triggered) D-FF, D Register JK-FF T-FF

25. Latches

26. D-Latch Block Diagram Symbol 4 inputs: D,E,Pre,Rst One output: Q D = Data Input E = Enable Input Pre = Preset Input Rst = Reset Input

27. D-Latch Truth Table DE dd100 dd011 d011 01110 11111 Symbol Truth Table

28. D-Latch State Equations DE dd100 dd011 d011 01110 11111 Symbol Equation (level clock) Truth Table

29. SR-Latch State Equations SR dd100 dd011 0011 01110 10111 1111??? Symbol Equation (level clock) Truth Table

30. Example T-FF D-FF D-Latch

31. Simulation

32. Flip-Flops

33. D-FF Positive Edge Triggered Block Diagram Symbol 4 inputs: D,Clk,Pre,Rst One output: Q D = Data Input Clk = Clock Input Pre = Preset Input Rst = Reset Input

34. D-FF Truth Table DClk dd100 dd011 d011 d111 0110 1111 Symbol Equation (rising clock) Truth Table

35. D-FF Truth Table DClk dd100 dd011 d011 d111 0110 1111 Symbol Equation (rising clock) Truth Table Pre= Preset Input (active low) Rst = Reset Input (active low) Highest priority

36. D-FF Truth Table DClk dd100 dd011 d011 d111 0110 1111 Symbol Equation (rising clock) Truth Table D = Data Input Clk = Clock input Qn = Register Output

37. D-FF Truth Table Qn follows D on Rising Edge of CLK DClk dd100 dd011 d011 d111 0110 1111 Symbol Equation (rising clock) Truth Table D = Data Input Clk = Clock input Qn = Register Output

38. T-FF (Toggle) Changes state on every tick of CLK TClk Dd100 Dd011 d011 d111 011 111 Symbol Equation (rising clock) Truth Table

39. SR-FF Set =>Qn=1 Reset=>Qn=0 SRClk ddd100 ddd011 dd011 dd111 0011 01110 10111 1111??? Symbol Equation (rising clock) Truth Table

40. JK-FF JKClk ddd100 ddd011 dd011 dd111 0011 01110 10111 1111 Symbol Equation (rising clock) Truth Table

41. Example: Design a JK-FF using only Logic and a D-FF JKClk ddd100 ddd011 dd011 dd111 0011 01110 10111 1111 Symbol Truth Table

42. Example State Diagram State Table Let s0=0 and s1=1

43. JK-FF Truth TableLogic Equations

44. Recall Moore FSM State Equations Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

45. JK Example Circuit Schematic F LogicD-Register H Logic (buffer) X input ns ps Block Diagram

46. JK Example Circuit Schematic Simulation

47. Memory

48.  We will add memory (or registers) to our logic circuits. This will allow us to design sequential circuits.

49. Registers  We will represent registers with the following block diagram Clock and reset are control signals Ns and ps are data signals