1. Module 1.3 Verilog Basics UNIT 1 : Introduction to Verilog Data Types

2. Value Set Verilog supports four values to model the functionality of real hardware. The four value levels are

3. Nets Nets represent connections between hardware elements. Nets are declared primarily with the keyword wire. Nets are one-bit values by default unless they are declared explicitly as vectors. The terms wire and net are often used interchangeably. The default value of a net is z (except the trireg net, which defaults to x ). Note that net is not a keyword but represents a class of data types such as wire, wand, wor, tri, triand, trior, trireg, etc. wire a; / / Declare net a for the above circuit

4. Registers Registers represent data storage elements. Registers retain value until another value is placed onto them. The default value for a reg data type is x. Register data types are commonly declared by the keyword reg. reg reset; // declare a variable reset that can hold its value NOTE : Do not confuse the term registers in Verilog with hardware registers built from edge-triggered flip-flops in real circuits. In Verilog, the term register merely means a variable that can hold a value.

5. Vectors Nets or reg data types can be declared as vectors (multiple bit widths). If bit width is not specified, the default is scalar (1-bit). Vector is defined as : wire [7:0] bus; / / 8-bit bus Usage : For the vector declarations shown above, it is possible to address bits or parts of vectors as shown below : busA[7] / / bit # 7 of vector busA

6. Integer An integer is a general purpose register data type used for manipulating quantities. Integers are declared by the keyword integer. Although it is possible to use reg as a general-purpose variable, it is more convenient to declare an integer variable for purposes such as counting. The default width for an integer is the host-machine word size, which is implementation specific but is at least 32 bits. integer counter; // general purpose variable used as a counter. initial counter = -1; // A negative one is stored in the counter

7. Real Real number constants and real register data types are decIared with the keyword real. They can be specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6, which is 3 x lo6 ). Real numbers cannot have a range declaration, and their default value is 0. real delta; // Define a real variable called delta initial begin delta = 4e10; // delta is assigned in scientific notation delta = 2.13; // delta is assigned a value 2.13 end

8. Time Data Types Verilog simulation is done with respect to simulation time. A special time register data type is used in Verilog to store simulation time. A time variable is declared with the keyword time. The width for time register data types is implementation specific but is at least 64 bits. The system function $time is invoked to get the current simulation time. time save-sim-time; // Define a time variable save-sim-time initial save-sim-time = $time; // Save the current simulation time

9. Arrays Arrays are allowed in Verilog for reg, integer, time, and vector register data types. Arrays are not allowed for real variables. Arrays are accessed by [ l. integer count[0:7]; // An array of 8 count variables reg bool[31:0]; //Array of 32 one-bit boolean register variables time chkqoint[l:l00]; //Array of 100 time checkpoint variables reg [4 : 0] port-id[0 : 7] ; //Array of 8port-ids; each port-id is 5 bits wide integer matrix[4:0][4:0]; // Illegal declaration. Multidimensional array. To use the array count[5] // 5th element of array of count variables

10. Parameters Verilog allows constants to be defined in a module by the keyword parameter. Parameters cannot be used as variables. parameter port-id = 5;//Defines a constant port-id parameter cache-line-width= 256; //constant defines width of cache line

11. Strings Strings can be stored in reg. The width of the register variables must be large enough to hold the string. Each character in the string takes up 8 bits (1 byte). Example : reg [8*18:1] string-value; //Declare a variable that is 18 bytes wide initial string-value = "Hello Verilog World"; / / String can be stored in variable

12. Special character Special characters serve a special purpose in displaying strings, such as newline, tabs and displaying argument values. Special characters can be displayed in strings only when they are preceded by escape characters