1. tag Cache Main memory Block 0 Block 1 Block 127 Block 128 Block 129 Block 255 Block 256 Block 257 Block 4095 Block 0 Block 1 Block 127 74Main memory address TagBlockWord Figure 5.15. Direct-mapped cache. 5

2. 4 tag Cache Main memory Block 0 Block 1 Blocki Block 4095 Block 0 Block 1 Block 127 12 Main memory address Figure 5.16. Associative-mapped cache. TagWord

3. tag Cache Main memory Block 0 Block 1 Block 63 Block 64 Block 65 Block 127 Block 128 Block 129 Block 4095 Block 0 Block 1 Block 126 tag Block 2 Block 3 tag Block 127 Main memory address664 TagSetWord Set 0 Set 1 Set 63 Figure 5.17. Set-associative-mapped cache with two blocks per set.

5. m bits Address in moduleMM address Figure 5.25. Addressing multiple-module memory systems. (b) Consecutive words in consecutive modules i k bits 0 Module MM address DBRABR DBRABRDBR Address in module (a) Consecutive words in a module i k bits Module DBRABRDBRABR DBR 0 2 k 1- n1- m bits

6. Page frame Virtual address from processor in memory Offset Virtual page numberPage table address Page table base register Figure 5.27. Virtual-memory address translation. Control bits Physical address in main memory PAGE TABLE Page frame +

7. Figure 5.28. Use of an associative-mapped TLB. No Yes Hit Miss Virtual address from processor TLB OffsetVirtual page number number Virtual pagePage frame in memory Control bits Offset Physical address in main memory Page frame =?

8. AluminumAcrylicLabel (a) Cross-section Polycarbonate plastic SourceDetectorSourceDetector SourceDetector No reflection Reflection PitLand 00010000100010010010 (c) Stored binary pattern Figure 5.32. Optical disk. PitLand 1 (b) Transition from pit to land