1. A Reconfigurable Accelerator Card for High Performance Computing Michael Aitken Supervisor: Prof M. Inggs Co-Supervisor: Dr A. Langman

2. Reconfigurable Co-processing

3. What is an accelerator card?

4. The Power of FPGAs Example: Virtex 5 – LX330T –331,000 Logic Cells –207,000 Flip-flops –11.6 Mb hardwired RAM –960 I/O pins –Theoretical I/O Bandwidth: 960 I/O pins at 800Mbps = 768 Gbps –24 On-board 3.2Gbps Transceivers giving 153.6 Gbps

5. Commercial Product – Celoxica RCHTX-XV4 (HPC Accelerator Card)‏ Cost: R60,000 + Courtesy: Celoxica

6. Why do we want our own accelerator? An advancement on existing cards: –Latest FPGAs available (Xilinx Virtex 5 – more logic, faster clock rate)‏ –Faster I/O interface needed for HPC (1 GE not good enough)‏ –Faster memory devices available –No: compulsory engineering costs, bundled software Core computing concept for the Advanced Computer Engineering Laboratory at the CHPC.

7. Methodology Background Investigation Conceptual Design Design Review and Adjustment Component Sourcing begins Schematic Capture Design Specification & Layout Outsourcing Gateware development PCB Fabrication and Assembly Testing

8. AMD’s Direct Connect Architecture Improved Latency Peripheral HTX device has direct access to system RAM via DMA

9. Conceptual Design

10. Power 30 – 50 Watts Over: 6 pin 12V connector or HTX 12V supply

11. Hierarchy Top Level Schematic

12. Hierarchy Low Level Schematic

13. Layout Design MTE, Pune India

14. Fabricated Board StreamLineCircuits, CA

15. Assembled Board Tellumat, Cape Town

16. QDRII+ Memory Tests

17. CX4 Connector Test: Differential Probe at 10GSa/s

18. XAUI TX over 0.5m cable

19. XAUI TX over 5m cable

20. CX4 Connector Test: Cable Loopback Test Status Bits indicate both cores are synchronized to all 4 incoming signals

21. HTX Interface Test Testing and Gateware to be done by Nick Thorne

22. Usage Scenario 1 Single Reconfigurable Node

23. Usage Scenario 2 Cluster Configuration 1

24. Usage Scenario 2 Cluster Configuration 2

25. Related work by other students Jane Hewitson – Preparing a FORTRAN processing engine Nick Thorne – Preparing a HyperTransport conroller core and drivers Brandon Hamiltion – Preparing the BORPH reconfigurable operating system

26. Questions?