1. DOM MB Status October 14, 2003 Gerald Przybylski Lawerence Berkeley National Laboratory GTPrzybylski 20/14/03 LBNL

2. A Rev 2 board IceCube Review GTPrzybylski 20/14/03 LBNL

3. Rev 3 Changes EPXA4 Baseline; EPC16 Config. Memory Memory Power Options (1.8V, 2.5V, 3.3V) Memory ‘Snubbing’ resistors Define ALL Memory Input Levels MoreMore Low impedance Power Distribution to SDRAM and SDRAM controller Primary Oscillator; Corning (Hi-Rel 2560A-0009) Alternate Oscillator; Toyocom IceCube Review GTPrzybylski 20/14/03 LBNL

4. More Rev 3 Changes Major Problem Component: - Al Electrolytic -> Polypropylene Film Power Filter Network Refinements Noise Related Layout Changes High-Rel DC-DC Converter by Power-One brand DC-DC Converter Footprint Options 4W or 7W dual footprint Simplify Input Power Protection HV Power Supply Connector Pin-out GTPrzybylski 20/14/03 LBNL

5. and More Rev 3 Changes Q/A Tests Added to Plan; Coupons on PCB 2 x 12 Channel ADCs vs. 1 x 8 Channel for housekeeping Hi-Rel Part Substitutions Test Connector (Main Cable and LC) Bill-of-Materials Consolidation IceCube Review GTPrzybylski 20/14/03 LBNL

6. Fabrication Changes Layout for Convenient Integration Restrict Layer Repairs during PCB Fab Temperature Cycling of Bare Boards Improve Process Control in PCB Fab Near Class-III Fab/Medical PCB Standards Tin – Awareness IceCube Review GTPrzybylski 20/14/03 LBNL

7. Tuning for Physics Performance On-Board Flasher Performance Tuning - UV LED gives < 10ns FWHM pulse - Blue LED gives ~13 ns FWHM pulse x0.25 x 2 x 8 gain for ATWD PMT inputs Extend Input Clipping Range [+2.4..-3.0] Stronger ATWD Drivers Optimize ATWD Driver Output Impedance to minimize ringing fADC channel gain adjustment for 12 bits GTPrzybylski 20/14/03 LBNL

8. Deletions SRAM ‘lookback-memory’ not needed since FPGA writes directly to SDRAM Test connector footprints not needed Alternate communications line receiver Lumped Delay Line… (space, performance) GTPrzybylski 20/14/03 LBNL

9. The End GTPrzybylski 20/14/03 LBNL

10. Memory Issues Improve Layout - Trace length matching - Bypassing - Low impedance power distribution (island) Match Output levels to Signal threshold Set-up Time Tuning (SD_CLKn -> SD_DQS0) Back GTPrzybylski 20/14/03 LBNL