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SOI pixel detector technology US-Japan collaboration Farah Khalid on behalf of ASIC Development Group SOIPIX collaboration people involved in SOIPIX: G.Deptuch, S.Holm, F.Khalid, R.Lipton, A.Shenai, M.Trimpl
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2 SOI Active Pixel Sensors (SOIAPS) work is one of Fermilab detector R&D directions Fully exploit advantages of the SOI technology for integrated circuits combined with a sensor monolithically Target for work at Fermilab: It is a great opportunity to develop solutions together with KEK and LAPIS Semiconductor (former OKI Semiconductor) Fermilab SOIPIX Collaboration Yasuo Arai
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3 Outstanding value of the SOIPIX collaboration is trusted and direct relation with the technology vendor Technology is based on commercial, voluminous 0.2 m CMOS process, which is indispensable for the electronics operating properly and having predictable and repetitive performance Exploration of SOI for pixel detectors Maturing of the technology, visible through significant extensions and modifications included into the original process, may eventually lead to a transition from pure research to use for specific applications SOIPIX: collaborative efforts seen from Fermilab Fermilab SOIPIX Collaboration
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at Fermilab: MAMBOs: Monolithic Active Pixel Sensors with Binary Counters 2006 MAMBOI 2.5×2.5 mm 2, 2008 MAMBOII 5×5 mm 2, 2010 MAMBO III (3D) 2×5×5 mm 2 and MAMBO IV 5×5 mm 2, 2011 MAMBO V 6x6 mm 2 resistive baising test structure 2.5×2.5 mm 2, OKI drift imager ASIC (2011 ) 3x6 mm 2 Fermilab’s SOI R&D with OKI process 7 prototype, pixel detectors have been submited over last 5 years, Mainstream: MAMBO : Monolithic Active Matrix with Binary Counters, and Research on alternative detector biasing
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BPW Nested BNW/BPW - electric potential under any circuitry may be kept constant or change very little only by voltage from integrated charge – gives increased C-to-V node capacitance – works with charge integrating pixels (3T-like), gain may be nonlinear, – charge injections due to electronics activity may be cancel out by sequential readout with exactly repeated patterns for control signals and CDS Major Fermilab Contribution: Nested Well structure Implemented collaboratively and successfully by LAPIS (OKI) in the SOI process – full isolation of the electronics and the detector charge collection node, – electric potential under any circuitry is kept constant (AC ground) – allows designs with amplification stages and virtual ground (CSA) – Removes parasitics feedbacks and instabilities, – Unfortunately increases input capacitance of CSA
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6 Fermilab SOIPIX Collaboration Purpose of the nested well structure – Tripple role of shielding between the SOI electronics and detector layer: to avoid back-gating in transistors (DC potential underneath the BOX shifts threshold of transistors), to avoid injection of parasitic charges from the SOI electronics to detector, to avoid strong electric field in BOX that results in accelerated radiation damage. Shielding: This well separates digital circuits from sensor substrate and prevents back gating effects This well collects the charge carriers SILVACO process simulatiom
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7 FZ 7.1 kΩcm ~485 m Multi-year program at Fermilab: Results from MAMBO IV Example of MAMBO IV results: no shift of NMOS transistor I DS /V GS in nested wells at back-gate biases ranging from 0 to full depletion 2 BNW Voltages used for illustration Explored HR FZ 7.1 kΩcm material and appeciated improved PDK and models Fermilab SOIPIX Collaboration Full depletion
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8 Details of MAMBO designs Fermilab SOIPIX Collaboration pixel design with window discriminator and per pixel counter MAMBO III, IV & V integrating CSA w/ pole-zero network, shaping filter CR-RC 2 with p =200ns; gain=~100 V/e -, ripple counter reconfigurable into shift register, DACs for threshold adjustment, control logic for testability
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9 Fermilab SOIPIX Collaboration single pixel (100µ x 100µ); ~950 transistors MAMBO III: vehicle for exploring bump-bonding with T-micro MAMBO III : Top chip: Electronics 5x5mm 2, 44x44 pixel matrix T-Micro: 3D Au-In µ-bump bonding – only one 3D chip received in March 2012, process seems to be maturing Bottom chip: matrix of detector pixels, no bond pads contains only micro bump pads, aligned with the top chip top chip: Pads with back metal opening
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10 Fermilab SOIPIX Collaboration SOI and 3D: (received March 2012) MAMBO III: 3D-bonded device, view from back-thinned side of electronics Aligned bonding targets Back-side deposited shielding metal pads TOP: Electronics BOTTOM: sensor
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11 Tests of MAMBO and other SOI device… Fermilab SOIPIX Collaboration National Instruments based tests setup - bought using US-Japan funds (ASIC tests WH14W)
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12 Fermilab SOIPIX Collaboration Tests of MAMBO V are progressing Major components of the signal processing chain are functional performed threshold scan of discriminators all 2600 pixels respond! (base-line restorer, trimming DAC, discriminators) First radiation events counting pixel device in SOI that is operational Progress of tests: Tests of MAMBO V DAC values varied from 0000 to 1111; Comparator changing state from 0 – 1 as the current in the comparator is steered between the two branches
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MAMBO V: Electronics (Received Feb 2012) First Image using 1mmTungsten Mask, 22kEv source Without depleting the detector mask
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SOI Collaboration Meeting, LBNL, 03/15/2012 Marcel Trimpl, Fermilab - 14 - 40um pixels 20um pixels Resistive biasing imager and past results random ghost hits Fe55-Image obtained with 2009 submission (based on Cz) - experienced high leakage current through bulk - No resistive biasing concept of resistive biasing - diode still p-in-n (e.g. here) - moderate voltage (around 10V) applied to backside - additional n-in-n rings biased to create drift field - collection time of 100ns in 250um detector: 10-15V on backside sufficient - n-ring(s) at front side create(s) additional lateral drift field to improve charge collection
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SOI Collaboration Meeting, LBNL, 03/15/2012 Marcel Trimpl, Fermilab New submission / New test setup Diode with BPW (20x20um pixel – 1 drift ring) - chip recently wire bonded to PCB - tests on basic operation of chip & RO chain in near future - waiting for chips with Fz substrate for more detailed studies new submission on Oct2011 run (6x3mm area) - Improved setup with dedicated PCB with fast analog buffers for 25MHz operation - cooling setup down to -40C (reduce/study leakage) Diode with BPW (40x40um pixel – 2 drift rings) - improved pixel circuitry - improved row/column operation -> to enable 25MHz pixel rate
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16 Some thoughts about forging SOIPIX… Some thoughts about growing detector R&D program now: The scientific contents of the SOIPIX activities is great, but to succeed we need to select and target applications that would exploit the advantages of the technology Resources, at Fermilab, are limited and currently generic R&D projects, like SOI pixels, may experience difficulties in prioritization Expected budgets are tight (real risk of ceasing some activities) Some thought on possible way of proceeding: Attempt sharing resources: design pieces and manpower Select some designs, e.g. X-ray imager or charged particle tracker, build specification and distribute design amongst participating institutions (one leader per design) Build and maintain library of blocks Perfecting device models (we experience severe convergence problems) Solving problem pertaining to parasitic extraction Fermilab SOIPIX Collaboration
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17 Significant developments have been made including: implementation of BPW nested BNW and BPW developed jointly with Fermilab for effective shielding enlargement of the reticle dimensions together with stitching of reticles for larger sensors and thinning and back-side processing. Among several applications which are of interest, large-surface detectors for soft X-ray (counting events or performing other dedicated functions, such as time of arrival) and detectors for tracking in HEP (but TID!) are particularly appealing Inter-institutional collaboration can be very efficient in these topical developments SOIPIX: Conclusions Fermilab SOIPIX Collaboration
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Thank you Fermilab Institutional Review, June 6-9, 2011 18
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