1. © Imperial College LondonPage 1 CERC Front End FPGA Development by Osman Zorba 12 May 2004 O. Zorba CALICE 12/05/2004

2. © Imperial College LondonPage 2 Progress Report O. Zorba CALICE 12/05/2004 ISE 6.2 and ChipScope Pro 6.2 licenses arrived during the 1 st week of May. LINKARRAY code has been incorporated (requires testing with CERC board). ADC readout order has been modified to reflect the VFE channels. LM82 I2C code integration has been investigated. (The code can be integrated into the current code with little effort). VFE in-line test board design. DAC Code testing – A number of slightly modified designs have been created to investigate the unexpected behaviour.

3. © Imperial College LondonPage 3 Future Work O. Zorba CALICE 12/05/2004 Test LINKARRAY code on the CERC board. Investigate and resolve the BUSY signal during the first 12 set of data. Integrate I2C Code. Test different designs for DAC control. Complete the in-line PCB design and manufacture.