1. IP Phone Chip System Design 邱垂民 CS group/EE R92921106 2004/6/15

2. Outline IP-Phone-Chip architecture and function VoIP SoC uPlatform Core architecture and function System Architecture of IP-Phone Software Device drivers and APIs coding uClinux Porting on SOHO gateway Reference

3. IP-Phone-Chip Development Board Block Diagram

4. Functional Description of IP- Phone-Chip The IP-Phone-Chip is a complete VoIP single-chip solution. And the network interface is implemented as an auto negotiating 10/100 Mbits/s Ethernet based LAN. This chip includes a complete three- port Ethernet subsystem implemented as a three-port switch (two external, one internal) with priority queuing running at 10/100 Mbits/s

5. IP-Phone-Chip Function Block Diagram Bridge & DMA AHB APB ARM9TDMI Core Instruction cache Instruction MMU Data Cache Data MMU Write Buffer Embedded ICE MIPS4Kc AMBA Bus I/F ARM9TDMI Core Instruction cache Instruction MMU Data Cache Data MMU Write Buffer Embedded ICE AMBA Bus I/F ARM9TDMI Core Instruction cache Instruction MMU Data Cache Data MMU Write Buffer Embedded ICE AMBA Bus I/F JTAG DSP Core AMBA Bus I/F Internal Memory HBI DSP TSI DSP Core AMBA Bus I/F Internal Memory HBI DSP TSI DSP Core AMBA Bus I/F Internal Memory HBI DSP TSI Reset CLOCK / PLL & POWER Reset CLOCK / PLL & POWER Internal SRAM Internal SRAM Serial Peripheral Interface RTC GPIO / Keypad controller GPIO / Keypad controller IRQ Controller Timer/Counter 2 Timer/Counter 1 Timer/Counter 0 Timer/Counter 2 Timer/Counter 1 Timer/Counter 0 Timer/Counter 2 Timer/Counter 1 Timer/Counter 0 UART 1 UART 0 UART 1 UART 0 UART 1 UART 0 Watchdog Timer EMIF SDRAM Controller SRAM Controller Flash Controller EMIF SDRAM Controller SRAM Controller Flash Controller SDRAM Controller SRAM Controller Flash Controller Ethernet DMA Ethernet DMA 10/100 Mbits/s three-port Ethernet Switch Controller 10/100 Mbits/s three-port Ethernet Switch Controller

6. Architecture Overview of VoIP SoC uPlatform Core The VoIP SoC uPlatform Core is an integration platform incorporating MIPS 4Kc to implement system-on-a-chip design. The VoIP SoC uPlatform Core is designed for meeting VoIP application that combines peripheral support functions, and follows the AMBA 2.0 on-chip-bus interface to link with. The VoIP SoC uPlatform Core also supports a wide range of memory type and the configurable peripherals to meet system-on-a-chip integration requirements.

7. Brief Specification of VoIP SoC uPlatform Core (1) AHB BUS CPU: MIPS4Kc 16Kbyte Instruction cache and 16Kbyte data cache. DSP: Improv’s 32-bit Jazz DSP. VLIW processor architecture. Jazz Host Bus Interface with AMBA Bus Wrapper 1 IRQ Controller 1 clock generator with PLL 1 Interrupt controller support external interrupt source External memory interface (EMI) for SDRAM, FLASH, SRAM devices JTAG test and debug control. Dual 10/100 Mbits/s Ethernet MACs. 10/100 Mbits/s three-port Ethernet switch (two external, one internal) with DMA. (TBD) PCI or USB for WLAN module (TBD)

8. Brief Specification of VoIP SoC uPlatform Core (2) APB BUS SPI: 1 SPI RTC: 1RTC with calendar Watchdog Timer: 1 Watchdog Timer UART: 1 UART GPIO: 4 ports/ 32 pins Timers/Counters: Two, 32-bit Timers/Counters Bridge: with 2channel DMA

9. System Architecture of SoC Software

10. Brief Specification of SoC Software Host Software: OS : MoataVista Linux Device drivers for IP-Phone Demonstration System DSP API ( Implemented by C Code) Jitter Buffer Control System Configuration & Management API (Implemented by C Code) Programming Tool Chain (Including Compiling Environment and Source Level Debugger) Supported library: Moatavista Lib Applications for Moatavista (including Busybox, shell) Supported File system: romfs, nfs, ramdisk TCP/IP protocol stack TFTP client, DHCP client Telnetd, httpd Supported VoIP Signaling: SIP (RFC3261), RTP DEMO Console-based and Web-based Configuration System Demo IP Phone Application supporting supplementary services

11. IP-Phone Demonstration System Keypad /LED JTAG HeaderDB9 MCU ICEUART/ Console WALL JACK Handset DSP ICE JTAG Header CPU + Peripheral IPs Main Board RJ45 RJ11 Jack Header Speaker -Phone PC LCD RJ45 Ether-Switch +MAC DB CODEC EB DSP DB Peripheral DB PHY EB stackable (AHB Extension) (APB Extension)

12. Device drivers and APIs coding Keypad/LED LCD DSP Ethernet

13. Brief Specification of DSP DSP Two-channels Voice processing software : Voice codecs: G.711, G.726 G.729a,, G.723.1 Acoustic echo cancellation with 64ms tail (TBD) Silence Suppression / Comfortable Noise Generation Tone Generation: DTMF, ringing, and call progress tones Voice Activity Detection Three-way conferencing (2 local 2 network) Automatic Gain Control

14. DSP driver (read data from HBI) VPS DSP HBI interface interrupt ISR DSP driver SIGIO Kernel mode User mode DSP API API_ISR Wrapper API VDB

15. DSP driver (write data to HBI) Wrapper API calls VPS_WriteChannelData() in DSP API, then DSP API writes the voice data into kernel mode, and DSP driver saves the data in the transmit_ring_buffer. When interrupted, ISR writes the data in transmit_ring_buffer into Rx_VDB.

16. Eth driver (1) esw_init_module() register_netdev() esw_init() switch_init() to set up ARL decision register(04h) to zero to disable all port first ether_setup() to assign some of the fields set MAC address in net_device data structure write MAC address to hardware via ARL decision register (30h, 34h) set net_device methods (open, stop, do_ioctl, get_stats, tx_timeout, hard_start_xmit) set net_device data members (watchdog_timeo, irq, dma)

17. Eth driver (2) esw_open() Disable esw irqs (ESW_IRQ_FS_RCV_OK, ESW_IRQ_TS_TX_OK, ESW_IRQ_TS_QUEUE_EMPTY, ESW_IRQ_FS_QUEUE_FULL) Register ESW init fs, ts ring buffers enable_irq() Start the transmit queue enable switch dma interrupts via BASE_ADDR_INT_REGS(04h) enable from-switch dma function via BASE_ADDR_DMA_REGS(04h) set up ARL decision register(04h) to ARL_DECISION_VALUE

18. Eth driver (3) esw_get_stats() return esw_private->esw_stats esw_tx_timeout() esw_show_state() to print some items for debugging esw_start_xmit() Check if there are enough space Calculate the TS descriptor entry Trigger the command unit resume (BASE_ADDR_DMA_REGS(00h) To Switch Enable)

19. Eth driver (4) esw_fs_rcv_ok_interrupt(): Packet from switch received OK Clear FS_RCV_OK status register bit by write 1 (BASE_ADDR_INT_REGS(00h)) Check for a rare out-of-memory case dev_alloc_skb(): allocate an skbuff for sending skb_reserve(): Align IP on 16 byte boundaries eth_type_trans(): Determine the packet's protocol ID netif_rx(): queues a received packet for the upper (protocol) levels to process enable from switch interrupt again

20. Eth driver (5) esw_ts_tx_ok_interrupt(): Packet to switch transmitted OK esw_ts_buffer_gc(): Free the original skb dev_kfree_skb_irq(): raise softirq esw_tsqe_interrupt(): TS Queue Empty Interrupt Clear TSQE status register bit by write 1 (BASE_ADDR_INT_REGS(00h)) netif_wake_queue(): test_and_clear_bit dev- >state

21. Eth driver (6) esw_fsqf_interrupt(): FS Queue Full Interrupt Clear FSQF status register bit by write 1 (BASE_ADDR_INT_REGS(00h)) esw_init_fs_desc_ring() init from switch (rx) ring write FS base addr and fssd to hardware (BASE_ADDR_DMA_REGS(14h,0Ch)) disable fs dma first enable from-switch dma function

22. Functions of SML

23. IP Phone Software Architecture Input Unit Call Unit Wrapper API Media Unit Display Unit Network Configuration Data IP Phone Software Architecture K200 SIP SML API LCD API Keypad API RTP Packet DSP API

24. uClinux Porting on SOHO gateway

25. Brief Specification of SOHO gateway The SOHO gateway inherit from Samsung4510A Fully 16/32-bit RISC architecture ARM7TDMI core JTAG-based debug solution External bus for ROM/SRAM, flash memory, DRAM and external I/O Unified Instruction/Data Cache Ethernet controller DMA engine with burst mode 100/10-Mbit per second operation DMA controller UARTs Timers Programmable I/O Interrupt controller

26. Steps of porting Download a uClinux distribution for Samsung 4510B Build ARM toolchain based on gcc-2.95.3 Modify some kernel files according to your platform Build the big endian kernel Using TRACE32 to download image file onto the SDRAM on SOHO gateway and debug the kernel

27. Build ARM toolchain based on gcc-2.95.3 Build form the tar balls Install binutils Install elf2flt Install genromfs Install gcc

28. Build kernel Make menuconfig Make dep Make lib_only Make user_only Make romfs Make image Make

29. Modify some kernel files include/asm/arch/hardware.h include/asm/arch/io.h include/asm/arch/irq.h include/asm/arch/irqs.h include/asm/arch/memory.h include/asm/arch/param.h include/asm/arch/system.h include/asm/arch/vmalloc.h …

30. Reference MontaVista Linux User’s Guide The Wookey’s “Porting the Linux Kernel to a New ARM platform” The Wookey’s “GNU Toolchain for ARM targets HOWTO”. Listing of GCC releases. Documents in the kernel source tree. google

31. Thank You!!