1. 1 IKI20210 Pengantar Organisasi Komputer Kuliah Minggu ke-4b: Bahasa Rakitan MIPS I diadaptasikan dari materi kuliah CS61C/2000 & CS152/1997  2000/1997 UCB 27 September 2002 Bobby Nazief (nazief@cs.ui.ac.id) Johny Moningka (moningka@cs.ui.ac.id) bahan kuliah: http://www.cs.ui.ac.id/~iki20210/

2. 2 Administratif: °Tugas PR: hari ini! °Jadwal Lab: daftarkan segera! Rabu & Kamis

3. 3 Review: AVR Assembler & AVR Studio

4. 4 Bahasa Rakitan MIPS I

5. 5 Salient features of MIPS I 32-bit fixed format inst (3 formats) 32 32-bit GPR (R0 contains zero) and 32 FP registers (and HI LO) partitioned by software convention 3-address, reg-reg arithmetic instr. Single address mode for load/store: base+displacement –no memory indirection, scaled –16-bit immediate plus LUI Simple branch conditions compare against zero or two registers for =,° no integer condition codes Delayed branch execute instruction after the branch (or jump) even if the branch is taken (Compiler can fill a delayed branch with useful work about 50% of the time)

6. 6 MIPS I Registers °Programmable storage 2^32 x bytes of memory 31 x 32-bit GPRs (R0 = 0) 32 x 32-bit FP regs (paired DP) HI, LO, PC

7. 7 MIPS Addressing Modes/Instruction Formats oprsrtrd immed register Register (direct) oprsrt register Base+index + Memory immedoprsrt Immediate immedoprsrt PC PC-relative + Memory All instructions 32 bits wide Register Indirect?

8. 8 MIPS arithmetic instructions InstructionExampleMeaningComments add add $1,$2,$3$1 = $2 + $33 operands; exception possible subtractsub $1,$2,$3$1 = $2 – $33 operands; exception possible add immediateaddi $1,$2,100$1 = $2 + 100+ constant; exception possible add unsignedaddu $1,$2,$3$1 = $2 + $33 operands; no exceptions subtract unsignedsubu $1,$2,$3$1 = $2 – $33 operands; no exceptions add imm. unsign.addiu $1,$2,100$1 = $2 + 100+ constant; no exceptions multiply mult $2,$3Hi, Lo = $2 x $364-bit signed product multiply unsignedmultu$2,$3Hi, Lo = $2 x $364-bit unsigned product divide div $2,$3Lo = $2 ÷ $3,Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3Lo = $2 ÷ $3,Unsigned quotient & remainder Hi = $2 mod $3 Move from Himfhi $1$1 = HiUsed to get copy of Hi Move from Lomflo $1$1 = LoUsed to get copy of Lo

9. 9 MIPS logical instructions InstructionExampleMeaningComment and and $1,$2,$3$1 = $2 & $33 reg. operands; Logical AND oror $1,$2,$3$1 = $2 | $33 reg. operands; Logical OR xorxor $1,$2,$3$1 = $2  $33 reg. operands; Logical XOR nornor $1,$2,$3$1 = ~($2 |$3)3 reg. operands; Logical NOR and immediateandi $1,$2,10$1 = $2 & 10Logical AND reg, constant or immediateori $1,$2,10$1 = $2 | 10Logical OR reg, constant xor immediate xori $1, $2,10 $1 = ~$2 &~10Logical XOR reg, constant shift left logicalsll $1,$2,10$1 = $2 << 10Shift left by constant shift right logicalsrl $1,$2,10$1 = $2 >> 10Shift right by constant shift right arithm.sra $1,$2,10$1 = $2 >> 10Shift right (sign extend) shift left logicalsllv $1,$2,$3$1 = $2 << $3 Shift left by variable shift right logicalsrlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable shift right arithm.srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

10. 10 MIPS data transfer instructions InstructionComment SW 500(R4), R3Store word SH 502(R2), R3Store half SB 41(R3), R2Store byte LW R1, 30(R2)Load word LH R1, 40(R3)Load halfword LHU R1, 40(R3)Load halfword unsigned LB R1, 40(R3)Load byte LBU R1, 40(R3)Load byte unsigned LUI R1, 40Load Upper Immediate (16 bits shifted left by 16) 0000 … 0000 LUI R5 R5

11. 11 Addressing Mode Usage? (ignore register mode) 3 programs measured on machine with all address modes (VAX) --- Displacement: 42% avg, 32% to 55% 75% --- Immediate: 33% avg, 17% to 43% 85% --- Register deferred (indirect): 13% avg, 3% to 24% --- Scaled: 7% avg, 0% to 16% --- Memory indirect: 3% avg, 1% to 6% --- Misc:2% avg, 0% to 3% 75% displacement & immediate 88% displacement, immediate & register indirect

12. 12 MIPS Compare and Branch °Compare and Branch BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative branch BNE rs, rt, offset <> °Compare to zero and Branch BLEZ rs, offsetif R[rs] <= 0 then PC-relative branch BGTZ rs, offset > BLT < BGEZ >= BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31) BGEZAL >= °Remaining set of compare and branch take two instructions °Almost all comparisons are against zero!

13. 13 Conditional Branch Addressing PC-relative since most branches are relatively close to the current PC address At least 8 bits suggested (± 128 instructions) Compare Equal/Not Equal most important for integer programs (86%)

14. 14 MIPS Compare and Set, Jump instructions InstructionExampleMeaning set on less thanslt $1,$2,$3if ($2 < $3) $1=1; else $1=0 Compare less than; 2’s comp. set less than immslti $1,$2,100if ($2 < 100) $1=1; else $1=0 Compare < constant; 2’s comp. set less than uns.sltu $1,$2,$3if ($2 < $3) $1=1; else $1=0 Compare less than; natural numbers set l. t. imm. uns.sltiu $1,$2,100if ($2 < 100) $1=1; else $1=0 Compare < constant; natural numbers jumpj 10000go to 10000 Jump to target address jump registerjr $31go to $31 For switch, procedure return jump and linkjal 10000$31 = PC + 4; go to 10000 For procedure call

15. 15 MIPS (RISC) vs. Intel 80x86 (CISC)

16. 16 Intel History: ISA evolved since 1978 °8086: 16-bit, all internal registers 16 bits wide; no general purpose registers; ‘78 °8087: + 60 Fl. Pt. instructions, (Prof. Kahan) adds 80-bit-wide stack, but no registers; ‘80 °80286: adds elaborate protection model; ‘82 °80386: 32-bit; converts 8 16-bit registers into 8 32-bit general purpose registers; new addressing modes; adds paging; ‘85 °80486, Pentium, Pentium II: + 4 instructions °MMX: + 57 instructions for multimedia; ‘97 °Pentium III: +70 instructions for multimedia; ‘99 °Pentium 4: +144 instructions for multimedia; '00

17. 17 MIPS vs. Intel 80x86 °MIPS: “Three-address architecture” Arithmetic-logic specify all 3 operands add $s0,$s1,$s2 # s0=s1+s2 Benefit: fewer instructions  performance °x86: “Two-address architecture” Only 2 operands, so the destination is also one of the sources add $s1,$s0 # s0=s0+s1 Often true in C statements: c += b; Benefit: smaller instructions  smaller code

18. 18 MIPS vs. Intel 80x86 °MIPS: “load-store architecture” Only Load/Store access memory; rest operations register-register; e.g., lw $t0, 12($gp) add $s0,$s0,$t0 # s0=s0+Mem[12+gp] Benefit: simpler hardware  easier to pipeline, higher performance °x86: “register-memory architecture” All operations can have an operand in memory; other operand is a register; e.g., add 12(%gp),%s0 # s0=s0+Mem[12+gp] Benefit: fewer instructions  smaller code

19. 19 MIPS vs. Intel 80x86 °MIPS: “fixed-length instructions” All instructions same size, e.g., 4 bytes simple hardware  performance branches can be multiples of 4 bytes °x86: “variable-length instructions” Instructions are multiple of bytes: 1 to 17;  small code size (30% smaller?) More Recent Performance Benefit: better instruction cache hit rates Instructions can include 8- or 32-bit immediates

20. 20 Instructions:MIPS vs. 80x86 °addu, addiu °subu °and,or, xor °sll, srl, sra °lw °sw °mov °li °lui °addl °subl °andl, orl, xorl °sall, shrl, sarl °movl mem, reg °movl reg, mem °movl reg, reg °movl imm, reg °n.a.

21. 21 80386 addressing (ALU instructions too) °base reg + offset (like MIPS) movl -8000044(%ebp), %eax °base reg + index reg (2 regs form addr.) movl (%eax,%ebx),%edi # edi = Mem[ebx + eax] °scaled reg + index (shift one reg by 1,2) movl(%eax,%edx,4),%ebx # ebx = Mem[edx*4 + eax] °scaled reg + index + offset movl 12(%eax,%edx,4),%ebx # ebx = Mem[edx*4 + eax + 12]

22. 22 Branch:MIPS vs. 80x86 °beq °bne °slt; beq °slt; bne °jal °jr $31 °(cmpl;) je if previous operation set condition code, then cmpl unnecessary °(cmpl;) jne °(cmpl;) jlt °(cmpl;) jge °call °ret

23. 23 RISC vs. CISC °RISC = Reduced Instruction Set Computer Term coined at Berkeley, ideas pioneered by IBM, Berkeley, Stanford °RISC characteristics: Load-store architecture Fixed-length instructions (typically 32 bits) Three-address architecture °RISC examples: MIPS, SPARC, IBM/Motorola PowerPC, Compaq Alpha, ARM, SH4, HP-PA,... °CISC = Complex Instruction Set Computer Term referred to non-RISC architectures °CISC characteristics: Register-memory architecture Variable-length instructions °RISC examples: Intel 80x86, VAX, IBM 360, …