1. Memory characteristics Ideal Access time (minimum). Nonvolatile. Stored data can be modified. Minimum space (very dense). Minimum current drain (power consumption). No memory meats all the requirements.

2. Memory types Mask- programmable ROM: –n address lines, 2 n memory locations, m data lines. –Fig 7-1 –programmed by placing diodes in the proper places. – programmed once at the factory according to the user truth table. –Should be mass production.

3. ROM Mask- programmable ROM: –n address lines, 2 n memory locations, m data lines. –programmed by placing diodes in the proper places. – programmed once at the factory according to the user truth table. –Should be mass production.

4. Field-Programmable ROMs One time programmable (OTP) ROM UV- light Erasable PROM (EPROM) Electrically Erased PROM: E 2 PROM –Flash Memory

5. One time programmable (OTP) ROM –Fusible link in series with diode –Selected fuses can be melted (blown) by the user giving logic 1.

6. UV- light Erasable PROM (EPROM): –Can be erased-reprogrammed many times. –Should be erased entirely before reprogramming. –Quartz window is placed on the top of the ceramic package containing the EPROM( why). –Erased by subjecting it for 15 min. to UV light of 2537 angstroms wavelength produced by commercial erasers. –These erasers can erase many EPROMS in the same time. – According to Intel, fluorescent (three years) or direct sunlight of one weak could erase it.

7. Programming (writing to) the EPROM –Programmers send the address for location to be programmed, its data, and pulse the PGM pin low for 100  s.

8. Disadvantages of the EPROM: –Should be removed from circuit board to be programmed –Byte eraser is not possible –The quartz window is expensive. Electrically Erased PROM: E 2 PROM –Can be programmed and erased in its place. –Both byte and bulk eraser modes are possible. –It has a lifetime : 10,000 to 1000,000 read/write cycles.

9. Flash Memory –as an EEPROM, it can be programmed and erased in its place –only bulk eraser modes are possible (entire or sub- block). –Simple cell compared to the traditional EEPROM. (then?) - Lowering cost - Improving reliability -Very dense memory part (then?) - small size -Where is it Used ? -Network cards, Laser printers, BIOS,…..

10. 32Mbit, 64Mbit, 128Mbit, 256Mbit, 512Mbit and 1Gbit. Erase Cycles1,000,000 times Data retention time10 years Read transfer> 750KB/second Write transfer> 450KB/second

11. RAM read & write volatile memory Workspace for the Microprocessor Temporary storage: keeps the operating system and the running applications, data and programs, while the power is on. When a file is loaded into memory, a copy of the file is loaded from the hard disk.

12. Basic RAM Types DRAM Dynamic RAM –INEXPENSIVE – MUST BE CONSTANTLY REFRESHED (recharged) – SLOW –Dense (high capacity) (hundreds of Mbytes) SRAM Static RAM – CACHE –FAST – EXPENSIVE –Capacity is much less than DRAM (few Kbytes)

13. FIGURE 7-8 Basic six-transistor static memory cell. (From J. Uffenbeck, Microcomputers and Microprocessors: The 8080, 8085, and Z-80. Prentice Hall, Englewood Cliffs, NJ, 1991.) John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e Copyright ©2002 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

14. SRAM Conventional SRAM is asynchronous. In these SRAMs the memory address is applied to the chip, the data appears on the output pins some time later (access time). It can be as fast as 15 ns. Modern SRAMs are SSRAMs SSRAM (Synchronous Static RAM) It will be discussed in 7.3

15. FIGURE 7-18 Basic read and write bus cycle timing for the 386, 486, and Pentium processors. Each bus cycle requires two T states. John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e Copyright ©2002 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

16. SSRAM timing

18. DRAM

21. Memory Chip Organization Organization is usually expressed as: Locations  width Example: 16 Mb ( 2 MB) can be found as any of these organizations: –16M  1 –16M  4 –16M  8 –16M  16 The minimum number of chips depends on the data bus of the processor. Example table 7.2

22. DRAM memory modules DRAM is the core memory for most of the microcomputer systems. DRAM chips are grouped in standard modules. SIMM (Single In line Memory Module) –30 pins, 1bytes ( Q. How many needed foe 486) –72 pins, 4 bytes ( Q. How many needed foe Pintium) DIMM (Dingle In line Memory Module) –168 pin (in both sides), 8 bytes – Suitable for Pentium

23. FIGURE 7-11 mory arrays are constructed by soldering DRAM chips to small circuit boards. The resulting component is referred to as a SIMM-single in-line memory module. 30- and 72-pin SIMMs are popular. John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e Copyright ©2002 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

24. FIGURE 7-12 Pinouts for an 8M x 32 (32 MB) SIMM. (Courtesy of Texas Instruments.) John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e Copyright ©2002 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

25. FIGURE 7-14 DIMM modules feature 168 pins-84 pins per module side. (Courtesy of Micron Technology, Inc.) John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e Copyright ©2002 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

26. FIGURE 7-15 DIMM memory module. Note the left and center keyways. John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e Copyright ©2002 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

27. RDRAM New DRAM technology which is not combatable with conventional DRAM Tech. Its chips are grouped in: RIMM Rambus In line Memory Module – 184 pins, 2 bytes Empty RIMM sockets to be populated with continuity modules.

28. FIGURE 7-16 Rambus memory system. Similar to DIMMs, RIMM modules are placed in RIMM sockets or connectors. Open slots must be terminated with RIMM continuity modules. (Courtesy of Rambus, Inc.) John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e Copyright ©2002 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.