2. 1 Chapter Four Register Transfer and Micro operations

3. 2 Contents 4-1 Register Transfer Language 4-2 Register Transfer 4-3 Bus and Memory transfers 4-4 Arithmetic Micro operations 4-5 Logic Micro operations 4-6 Shift Micro operations 4-7 Arithmetic logic shift unit

4. 3 Register Transfer Language The set of register it contains and their functions. The sequence of micro operations performed on the binary information stored in the register. The control that initiated the sequence of micro operations.

5. 4 Figure 4-1 Block diagram of register R1 R2 7 6 5 4 3 2 1 0 PC(H) PC(L) 15 0 07815 Showing individual bitsRegister R Divide into two partsNumbering of bits

6. 5 Figure 4-2 Transfer from R1 to R2 P: R2 R1 R2 Control circuit Load P n Clock R1

7. 6 Figure 4-2 b Timing diagram Clock t t+1 load Transfer occurs here

8. 7 Table 4-1 Basic symbols for register transfer SymbolDescriptionExamples Letters (and numerals) Parentheses ( ) Arrow Comma, Denotes a register Denotes a part of a register Denotes transfer of information Separates two micro operations MAR, R2 R2(0-7),R2(L) R2 R1 R2 R1, R1 R2

9. 8 Figure 4-3 BUS AND MEMORY TRANSFER 4 – L I N E C O M M O N B U S 3 2 1 0 4 x 1 M U X 0 3 2 1 0 D 0 C 0 B 0 A 0 4 x 1 M U X 1 3 2 1 0 4 x 1 M U X 2 3 2 1 0 4 x 1 M U X 3 3 2 1 0 D 1 C 1 B 1 A 1 D 2 C 2 B 2 A 2 3 2 1 0 A 2 A 1 A 0 B 2 B 1 B 0 C 2 C 1 C 0 D 2 D 1 D 0 REGISTER CREGISTER AREGISTER BREGISTER D S 1 S0

10. 9 Table 4-2 Function table for bus s1s1 s2s2 Register selected A B C D 0 0 1 1 0 1

11. 10 Figure 4-4 Graphical symbol for Three-state Bus Buffers Normal input A Control input C Output Y=A if C=1 High-impedance if C=0

12. 11 Figure 4-5 Bus line with three state-buffers Bus line for bit 0 A0 A0 B0 B0 C0 C0 D0 D0 Select Enable 0 1 2 3 2 x 4 Decoder S0 E

13. 12 Memory Transfer Read: DR M[AR] Write: M[AR] R1

14. 13 Arithmetic Micro operations Register transfer micro operations transfer binary information from one register to another. Arithmetic micro operation performs arithmetic operations on numeric data stored in register. Logic micro operations perform bit manipulation operations on nonnumeric data stored in register. Shift micro operations perform shift operations on data stored register.

15. 14 Table 4-3 Arithmetic Micro operation Symbolic designation Description R3 R1+ R2 R3 R1- R2 R2 R2 R2 + 1 R3  R1+ R2 + 1 R1 R1 + 1 R1 R1 - 1 Contents of R1 plus R2 transferred to R3 Contents of R1 minus R2 transferred to R3 Complement the contents of R2( 1’s complement) 2’s complement the contents of R2(negate) R1 plus the2’s complement of R2(subtraction) Increment the contents of R1 by one Decrement the contents of R1 by one

16. 15 Figure 4-6 4 – Bit binary adder FA A0A0 B0B0 C0C0 S0S0 S1S1 S2S2 S3S3 C4C4 A1A1 B1B1 B2B2 B3B3 A2A2 A3A3 C1C1 C2C2 C3C3

17. 16 Figure 4-7 4 – bit adder subtractor FA C0C0 C1C1 C2C2 C3C3 C4C4 S3S3 S2S2 S1S1 S0S0 A0A0 B0B0 A1A1 B1B1 B2B2 B3B3 A2A2 A3A3 M

18. 17 Figure 4-8 4 – Bit binary Incrementer HA CCCCSSSS S0S0 S1S1 S2S2 S3S3 C4C4 x y A 0 1 A1A1 A2A2 A3A3

19. 18 S1 S0 0 1 2 3 S1 1 3 2 0 S0 Figure 4-9 4-bit arithmetic circuit C in S0 S1 A0 B0 B1 B2 B3 Xo Co X1 C1 X2 C2 X3 C3 Do D1 D2 D3 Cout yo C1 y1 C2 y2 C3 y3 C4 01 S1 1 3 2 0 S0 S1 1 3 2 0 S0 4 x 1 MUX 4 x 1 MUX 4 x 1 MUX 4 x 1 MUX

20. 19 Table 4-4 Arithmetic circuit function table Select S 1 S 0 C in InputOutput D = A + Y + C in Y Micro operation 0000111100001111 0011001100110011 0101010101010101 BBBB0011BBBB0011 D = A + B D = A + B + 1 D = A + B D = A + B + 1 D = A D = A + 1 D = A - 1 D = A Add Add with carry Subt. with borrow Subtract Transfer A Increment A Decrement A Transfer A

21. 20 Table 4 – 5 Truth table for 16 Function of two variables 00110011 01010101 00000000 00010001 00100010 00110011 01000100 01010101 01100110 01110111 10001000 10011001 10101010 10111011 11001100 11011101 11101110 11111111 x yF 0 F 1 F 2 F 3 F 4 F 5 F 6 F 7 F 8 F 9 F 10 F 11 F 12 F 13 F 14 F 15

22. 21 TABLE 4-6 SIXTEEN LOGIC MICRO OPERATIONS Boolean function Micro operationsName F0 = 0F  0Clear F1 = xyF  A ^ BAnd F2 = xy’F  A ^ B F3 = xF  ATransfer A F4 = x’yF  A ^ B F5 = yF  BTransfer B F6 = x y F  A B Exclusive-or F7 = x + yF  A ٧ BOR F8 = (x + Y)’F  A V BNOR F9 = (x Y)’F  A BExclusive-NOR F10 = y’F  BComplement B F11 = x + y ‘F  A V B F12 = x’F  AComplement A F13 = x’ + yF  A v B F14 = (xy)’F  A ^ BNAND F15 = 1 F  all 1’s Set to all 1’s

23. 22 Figure 4-10 One stage of logic circuit 4x1 MUX S1 S0OutputOperation 00110011 01010101 E = A v B E = A ^ B E = A B E = A AND OR XOR COMPLEMENT E i S1 S0 A i B i 0 1 2 3

24. 23 Figure 4-12 4-bit combinational circuit shifter 0101 S S S S 0101 0101 0101 Mux 0101 Select S Output H0H0 H0H0 H1H1 H2H2 H3H3 H1H1 H2H2 H3H3 IRA1IRA1 A0A2A0A2 A1A3A1A3 A2IlA2Il Ao A1 A3 A4 Serial input (IL) Serial input (IR) Select 0 for shift right 1 for shift left

25. 24 Figure 4-13 One stage of arithmetic logic shift unit Select 01230123 DiDi EiEi shr shl A i -1 A i+1 AiAi BiBi CiCi C i +1 S0 S1 S2 S3 One stage of logic circuit One stage of arithmetic circuit F i 4 x 1 MUX

26. 25 Operation Select S0S0 S1S1 S2S2 S3S3 C in OperationFunction 0000000000001100000000000011 0000000011110100000000111101 000011110011xx000011110011xx 001100110101xx001100110101xx 01010101xxxxxx01010101xxxxxx F = A F = A + 1 F = A + B F = A + B +1 F = A + B F = A + B + 1 F = A -1 F = A F = A ^ B F = A v B F = A B F = A F = shr A R = shl A Transfer A Increment A Addition Add with carry Subtract with borrow Subtraction Decrement A Transfer A AND OR XOR Complement A Shift right A into F Shift left A into F Table 4-8 Function table for arithmetic logic shift unit