1. 1  1998 Morgan Kaufmann Publishers Machine Instructions: Language of the Machine Lowest level of programming, control directly the hardware Assembly instructions are symbolic versions of machine instructions More primitive than higher level languages Very restrictive Programs are stored in the memory, one instruction is fetched and executed at a time We’ll be working with the MIPS instruction set architecture

2. 2  1998 Morgan Kaufmann Publishers MIPS instruction set: Load from memory Store in memory Logic operations –and, or, negation, shift,... Arithmetic operations –addition, subtraction,... Branch

3. 3  1998 Morgan Kaufmann Publishers Instruction types: 1 operand Jump #address Jump $register number 2 operands Multiply $reg1, $reg2 3 operands Add $reg1, $reg2, $reg3

4. 4  1998 Morgan Kaufmann Publishers MIPS arithmetic Instructions have 3 operands Operand order is fixed (destination first) Example: C code: A = B + C MIPS code:add $s0, $s1, $s2 $s0, etc. are registers (associated with variables by compiler)

5. 5  1998 Morgan Kaufmann Publishers MIPS arithmetic Design Principle 1: simplicity favours regularity. Of course this complicates some things... C code: A = B + C + D; E = F - A; MIPS code: add $t0, $s1, $s2 add $s0, $t0, $s3 sub $s4, $s5, $s0 Operands must be registers, 32 registers provided Design Principle 2: smaller is faster.

6. 6  1998 Morgan Kaufmann Publishers Registers vs. Memory ProcessorI/O Control Datapath Memory Input Output Arithmetic instructions operands are registers. Compiler associates variables with registers. What about programs with lots of variables? Memory!

7. 7  1998 Morgan Kaufmann Publishers Memory Organization Viewed as a large, single-dimension array, with an address. A memory address is an index into the array. "Byte addressing" means that the index points to a byte of memory. 0 1 2 3 4 5 6... 8 bits of data

8. 8  1998 Morgan Kaufmann Publishers Memory Organization Bytes are nice, but most data items use larger "words”. For MIPS, a word is 32 bits or 4 bytes. 2 32 bytes with byte addresses from 0 to 2 32 -1 2 30 words with byte addresses 0, 4, 8,... 2 32 -4 Words are aligned, i.e., the 2 least significant bits of a word address are equal to 0. –Not in all architectures! 0 4 8 12... 32 bits of data Registers hold 32 bits of data.

9. 9  1998 Morgan Kaufmann Publishers Load and store instructions Example: C code: A[8] = h + A[8]; MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 32($s3) $s3 contains the base of the array. $s2 contains h. Word offset 8 equals byte offset 32. Store word has destination last. Remember arithmetic operands are registers, not memory!

10. 10  1998 Morgan Kaufmann Publishers So far we’ve learned: MIPS — loading and storing words but addressing bytes — arithmetic on registers only InstructionMeaning add $s1, $s2, $s3$s1 = $s2 + $s3 sub $s1, $s2, $s3$s1 = $s2 – $s3 lw $s1, 100($s2)$s1 = Memory[$s2+100] sw $s1, 100($s2)Memory[$s2+100] = $s1

11. 11  1998 Morgan Kaufmann Publishers Instructions, like registers and words of data, are also 32 bits long. Example: add $t0, $s1, $s2 R-type instruction Format: 00000010001100100100000000100000 op rs rt rdshamtfunct opopcode, basic operation rs1st source reg. rt2nd source reg. rddestination reg shamtshift amount (in shift instructions) functfunction, selects the specific variant of the operation Machine Language

12. 12  1998 Morgan Kaufmann Publishers Introduce a new type of instruction format –I-type for data transfer instructions Example: lw $t0, 32($s2) 35 18 9 32 op rs rt 16 bit number rt = destination register address range =  2 15 B =  2 13 words new instruction format but fields 1…3 are the same Design principle 3: Good design demands good compromises Machine Language

13. 13  1998 Morgan Kaufmann Publishers Instructions are groups of bits Programs are stored in memory — to be read or written just like data Fetch & Execute Cycle –Instructions are fetched and put into a special register –Bits in the register "control" the subsequent actions –Fetch the “next” instruction and continue ProcessorMemory memory for data, programs, compilers, editors, etc. Stored Program Concept

14. 14  1998 Morgan Kaufmann Publishers Decision making instructions –alter the control flow, –i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne $t0, $t1, Label # branch if not equal beq $t0, $t1, Label # branch if equal Example (if): if (i==j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label:.... Control

15. 15  1998 Morgan Kaufmann Publishers MIPS unconditional branch instructions: j label Example (if - then - else): if (i!=j) beq $s4, $s5, Label1 h=i+j; add $s3, $s4, $s5 else j Label2 h=i-j;Label1: sub $s3, $s4, $s5 Label2:... Control

16. 16  1998 Morgan Kaufmann Publishers Example (loop): Loop: ---- i=i+j; if(i!=h) go to Loop --- Loop: --- add $s1, $s1, $s2 #i=i+j bne $s1, $s3, Loop --- Control

17. 17  1998 Morgan Kaufmann Publishers So far: Instruction Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 – $s3 lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1 bne $s4,$s5,L Next instr. is at Label if $s4  $s5 beq $s4,$s5,L Next instr. is at Label if $s4 = $s5 j Label Next instr. is at Label Formats: the 16 b and 26 b addresses are word addresses op rs rt rdshamtfunct op rs rt 16 bit address op 26 bit address RIJRIJ

18. 18  1998 Morgan Kaufmann Publishers We have: beq, bne, what about Branch-if-less-than? New instruction: set on less than if $s1 < $s2 then $t0 = 1 slt $t0, $s1, $s2 else $t0 = 0 slt and bne can be used to implement branch on less than slt $t0, $s0, $s1 bne $t0, $zero, Less Note that the assembler needs a register to do this, there are register conventions for the MIPS assembly language we can now build general control structures Control Flow

19. 19  1998 Morgan Kaufmann Publishers MIPS Register Convention $at, 1 reserved for assembler $k0, $k1, 26-27 reserved for operating system $t0…$t7, $t8, $t9 subroutine does not save $s0…$s7 subroutine saves if uses

20. 20  1998 Morgan Kaufmann Publishers Procedures and subroutines allow reuse and structuring of code Steps –Place parameters in a place where the procedure can access them –Transfer control to the procedure –Acquire the storage needed for the procedure –Perform the desired task –Place the results in a place where the calling program can access them –Return control to the point of origin Procedure calls

21. 21  1998 Morgan Kaufmann Publishers $a0...$a3four argument registers for passing parameters $v0...$v1two return value registers $rareturn address register use of argument and return value register: compiler handling of control passing mechanism: machine jump and link instruction:jal ProcAddress –saves return address (PC+4) in $ra (Program Counter holds the address of the current instruction) –loads ProcAddress in PC return jump:jr $ra –loads return address in PC Register assignments for procedure calls

22. 22  1998 Morgan Kaufmann Publishers Used if four argument registers and two return value registers are not enough or if nested subroutines (a subroutine calls another one) are used Can also contain temporary data The stack is a last-in-first-out structure in the memory Stack pointer ($sp) points at the top of the stack Push and pop instructions MIPS stack grows from higher addresses to lower addresses Stack

23. 23  1998 Morgan Kaufmann Publishers bottom top in out elements in the stack SP stack grows elements in the stack Stack and Stack Pointer

24. 24  1998 Morgan Kaufmann Publishers Small constants are used quite frequently e.g., A = A + 5; B = B - 1; Solution 1: put constants in memory and load them To add a constant to a register: lw $t0, AddrConstant($zero) add $sp,$sp,$t0 Solution 2: to avoid extra instructions keep the constant inside the instruction itself addi $29, $29, 4 # i means immediate slti $8, $18, 10 andi $29, $29, 6 Design principle 4: Make the common case fast. Constants

25. 25  1998 Morgan Kaufmann Publishers We'd like to be able to load a 32 bit constant into a register Must use two instructions, new "load upper immediate" instruction lui $t0, 1010101010101010 Then must get the lower order bits right, i.e., ori $t0, $t0, 1010101010101010 10101010101010100000000000000000 1010101010101010 ori 10101010101010100000000000000000 filled with zeros How about larger constants?

26. 26  1998 Morgan Kaufmann Publishers simple instructions all 32 bits wide very structured, no unnecessary baggage only three instruction formats rely on compiler to achieve performance — what are the compiler's goals? help compiler where we can op rs rt rdshamtfunct op rs rt 16 bit address op 26 bit address RIJRIJ Overview of MIPS

27. 27  1998 Morgan Kaufmann Publishers Instructions: bne $t4,$t5,Label Next instruction is at Label if $t4  $t5 beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5 j Label Next instruction is at Label Formats: Addresses are not 32 bits op rs rt 16 bit address op 26 bit address I Addresses in Branches and Jumps J

28. 28  1998 Morgan Kaufmann Publishers Instructions: bne $t4,$t5,Label Next instruction is at Label if $t4  $t5 beq $t4,$t5,Label Next instruction is at Label if $t4=$t5 Format: We need 32 bit addresses; use PC-relative addressing –add the 16-bit address (2’s complement number) to the PC; –most branches are local, so 16-bit offset or  2 15 word (  128 kB) address range is usually enough op rs rt 16 bit address I Addresses in Branches

29. 29  1998 Morgan Kaufmann Publishers Instruction: j Label Next instruction is at Label Format: To get a 32 bit address the upper bits of the PC are concatenated with the 26-bit address 2 26 word (256 MB) address range if range is not enough, use the jr instruction (not discussed in detail) jr Register Addresses in Jumps J op 26 bit address

30. 30  1998 Morgan Kaufmann Publishers Register addressing –operand in a register Base or displacement addressing –operand in the memory –address is the sum of a register and a constant in the instruction Immediate addressing –operand is a constant within the instruction PC-relative addressing –address is the sum of the PC and a constant in the instruction –used e.g. in branch instructions Pseudodirect addressing –jump address is the 26 bits of the instruction concatenated with the upper bits of the PC MIPS addressing mode summary

31. 31  1998 Morgan Kaufmann Publishers MIPS addressing mode summary

32. 32  1998 Morgan Kaufmann Publishers Direct addressing –operand in the memory –address in the instruction Register indirect addressing –operand in the memory –address in a register Implied addressing –operand location specified by the operation code Used in other computers Additional addressing modes

33. 33  1998 Morgan Kaufmann Publishers To summarize:

34. 34  1998 Morgan Kaufmann Publishers Assembly provides convenient symbolic representation –much easier than writing down numbers –e.g., destination first Machine language is the underlying reality –e.g., destination is no longer first Assembly can provide 'pseudoinstructions' –e.g., “move $t0, $t1” exists only in Assembly –would be implemented using “add $t0,$t1,$zero” When considering performance you should count real instructions Assembly Language vs. Machine Language

35. 35  1998 Morgan Kaufmann Publishers Design alternative: –provide more powerful operations than found in MIPS –goal is to reduce number of instructions executed –danger is a slower cycle time and/or a higher CPI Sometimes referred to as “RISC vs. CISC” –Reduced Instruction Set Computers –Complex Instruction Set Computers –virtually all new instruction sets since 1982 have been RISC Alternative Architectures

36. 36  1998 Morgan Kaufmann Publishers Reduced Instruction Set Computers Common characteristics of all RISCs –Single cycle issue –Small number of fixed length instruction formats –Load/store architecture –Large number of registers Additional characteristics of most RISCs –Small number of instructions –Small number of addressing modes –Fast control unit

37. 37  1998 Morgan Kaufmann Publishers An alternative architecture: 80x86 1978: The Intel 8086 is announced (16 bit architecture) 1980: The 8087 floating point coprocessor is added 1982: The 80286 increases address space to 24 bits, +instructions 1985: The 80386 extends to 32 bits, new addressing modes 1989-1995: The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance) 1997: MMX is added

38. 38  1998 Morgan Kaufmann Publishers An alternative architecture: 80x86 Intel had a 16-bit microprocessor two years before its competitors’ more elegant architectures which led to the selection of the 8086 as the CPU for the IBM PC “This history illustrates the impact of the “golden handcuffs” of compatibility” “an architecture that is difficult to explain and impossible to love”

39. 39  1998 Morgan Kaufmann Publishers A dominant architecture: 80x86 See your textbook for a more detailed description Complexity: –Instructions from 1 to 17 bytes long –one operand must act as both a source and destination –one operand can come from memory –complex addressing modes e.g., “base or scaled index with 8 or 32 bit displacement” Saving grace: –the most frequently used architectural components are not too difficult to implement –compilers avoid the portions of the architecture that are slow

40. 40  1998 Morgan Kaufmann Publishers Instruction complexity is only one variable –lower instruction count vs. higher CPI / lower clock rate Design Principles: –simplicity favours regularity –smaller is faster –good design demands good compromises –make the common case fast Instruction set architecture –a very important abstraction indeed! Summary