1.  Program Slicing : Analysis technique of extracting parts of a given program, relevant to the aspects being analyzed (the slicing criterion). E.g. slicing criterion : slice : subset of the statements in the program that affect the variable at that line number.  Applications  Debugging  Component Extraction  Maintenance  State Space Reduction in Formal Verification VHDL Slicer Design and Implementation of a Slicer for VHDL Programs.

2. 1) read(n); 2) i:=1; 3) sum := 0; 4) product :=1; 5) while i<=n do { 6) sum :=sum +i; 7) product:=product * i; 8) i := i +1; } 9) write(sum); 10) write(product); Slicing criterion: 1) read(n); 2) i:=1; 3) 4) product :=1; 5) while i<=n do { 6) 7) product:=product * i; 8) i := i +1; } 9) 10) write(product); slice wrt ;

3. VHDL Program Reduced VHDL Program "Slice" Output Signal "Slicing Criterion" VHDL Slicer  Slicing Criterion for VHDL Programs : An output signal (s).  Requirements : For any input vector the behaviour of the slice, w.r.t. signal s should be identical to that of the original program.

4. VAUL cfg_gendflow_analyzer cdg_gen AST CFG CDS DDS PDG VHDL Program Entity1.PDG Entity2.PDG EntityN.PDG SDG reachability Slicing criterion Reduced SDG code_gen Sliced VHDL Program VAUL : VHDL Analyzer and Utility Library AST : Abstract Syntax TreePDG : Program Dependence Graph CFG : Control Flow GraphSDG : System Dependence Graph DDS : Data Dependence SubGraph CDS : Control Dependence SubGraph

5. Entity adder is Architecture rtl of adder is port(a,b,cin : in bit; s<= a xor b; sum,cout : out bit;)sum<= s xor cin; End addercout <= (a and b) or (s and cin); end rtl; Program Dependence Graph :