1. Technical University Tallinn, ESTONIA Overview about Testing of Digital Systems 0110 T 6 0010011 Fault table Test generation Fault simulation Fault modeling Test experiment data Testing How many rows and columns should be in the Fault Table? 1 FaultF 5 located Fault diagnosis

2. Technical University Tallinn, ESTONIA Transistor Level Faults Stuck-at-1 Broken (change of the function) Bridging Stuck-open (change of the number of states) Stuck-on (change of the function) Short (change of the function) Stuck-off (change of the function) Stuck-at-0 Logic level interpretations:

3. Technical University Tallinn, ESTONIA Structural Logic Level Fault Modeling 1 x2x2 x1x1 Broken line 1 x2x2 x1x1 Bridge to ground 0V Stuck-at-0 Stuck-at fault model: Stuck-at-1 & x2x2 x1x1 Broken line 1 x2x2 x1x1 Bridge to Power Supply V dd Why logic fault models? complexity of simulation reduces (many physical faults may be modeled by the same logic fault) one logic fault model is applicable to many technologies logic fault tests may be used for physical faults whose effect is not completely understood they give a possibility to move from the lower physical level to the higher logic level

4. Technical University Tallinn, ESTONIA Testing of Bridging Fault Models Wired AND model x1x1 x2x2 x’ 1 x’ 2 & x1x1 x2x2 x’ 1 x’ 2 W-AND: 4 & X 1 = 1 & X 3 = 1  0 y 1 = 1  0 X 2 = 1 0  1 & X 4 = 0 X 5 = 1 y 2 = 1

5. Technical University Tallinn, ESTONIA Testing of Bridging Fault Models Wired OR model x1x1 x2x2 x’ 1 x’ 2 1 x1x1 x2x2 x’ 1 x’ 2 W-OR: 5 & X 1 = 1 & X 4 = 0  1 y 2 = 1  0 X 2 = 1 0 & X 3 = 1 X 5 = 1 y 1 = 1

6. Technical University Tallinn, ESTONIA Delay Fault Models Delay faults are tested by test pattern pairs: 1) F irst pattern initializes circuit 2) Second pattern sensitizes the fault Fault models: - Gate delay fault (delay fault is lumped at a single gate, quantitative model) - Transition fault (qualitative model, gross delay fault model, independent of the activated path) - Path delay fault (sum of the delays of gates along a given path) - Line delay fault (is propagated through the longest senzitizable path) - Segment delay fault (tradeoff between the transition and the path delay fault models) 6 & & & 00 & A C B x1x1 x2x2 x3x3 10 1 01 11 110 001 D D CL Clock

7. Technical University Tallinn, ESTONIA Structural Test Generation Fault detection A test t = 1101 is simulated, both without and with the fault a/0 The fault is detected since the output values in the two cases are different Why is fault detected? A fault a/0 is sensitized by the value 1 on a line a A path from the faulty line a is sensitized (bold lines) to the primary output Structural gate-level testing: fault sensitization 00

8. Technical University Tallinn, ESTONIA Testing of Inputs 1 & & 1 a b y a1a1 b a2a2 11 0 1 No test for  0 0 & & 1 a b y a1a1 b a2a2 10 1 1 No test for  1 0 & & 1 a b y a1a1 b a2a2 00 1 1 Test for  1

9. Technical University Tallinn, ESTONIA Testing of Inputs 1 & & 1 a b y a1a1 b a3a3 1 1 0 1 No test for  0 & c a2a2 c 0 0

10. Technical University Tallinn, ESTONIA Fault Simulation with Critical Path Tracing & & 1 1 1 2 3 4 5 a c b 1 1 0 0 0 0 0 1 1 y Problems : & & 1 1 1 1/01/0 y & & 1 0 1 1 y 1/0 1 1 1/01/0 1 1 The critical path is not continuous The critical path breaks on the fan-out Activated (critical) path is traced backwards

11. Research in ATI © Raimund Ubar Topological view on Binary Decision Diagrams: BDDs and Testing of Logic Circuits 11

12. Research in ATI © Raimund Ubar BDDs for an 8-bit data selector BDDs and Complexity  S.Minato, 1996

13. Research in ATI © Raimund Ubar Each node in SSBDD represents a signal path: Mapping Between Circuit and SSBDD x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 0 1 0 1 13 Signal path Node x 11 in SSBDD represents the path ( x 1, x 11, x 6, y ) in the circuit The SAF-0(1) fault at the node x 11 represents the SAF faults on the lines x 11, x 6, y in the circuit  fault collapsing 32 faults (16 lines) in the circuit  16 faults (8 nodes) in SSBDD

14. Technical University Tallinn, ESTONIA Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 1 0 1 1 1 Test pattern: x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0 Tested faults: x 12  0, x 31  0, x 4  0 Testing Stuck-at-0 faults on paths:

15. Technical University Tallinn, ESTONIA BIST: Pseudoexhaustive Testing Pseudo-exhaustive test sets: –Output function verification maximal parallel testability partial parallel testability –Segment function verification Output function verification 2 16 = 65536 Exhaustive test Primitive polynomials Pseudo- exhaustive parallel > 16 Pseudo- exhaustive sequential >> 4x16 = 64 4 4 4 4 Segment function verification F & 1111 0101 0011 0101 0011

16. Technical University Tallinn, ESTONIA Testing ripple-carry adder Output function verification (maximum parallelity) Exhaustive test generation for n-bit adder: Good news: Bit number n - arbitrary Test length - always 8 (!) 0-bit testing 2-bit testing 1-bit testing 3-bit testing … etc Bad news: The method is correct only for ripple-carry adder

17. Research in ATI © Raimund Ubar Test Pairs for Multiple Fault Testing To test a path under any multiple faults, two pattern test is needed  &  & 0  11 1010 0101 0101 00 a b c d Testing of multiple faults by pairs of patterns b  1 Tested path for b  1/0 00 11 The lower path from b is under test A pair of patterns is applied on b 0101 Two general approaches for testing: Devil’s approach – to detect a fault Angel’s approach – to prove correctness (the absence of a fault)

18. Research in ATI © Raimund Ubar Test Pairs for Multiple Fault Testing To test a path under any multiple faults, two pattern test is needed  &  & 0  11 11/00 10/11 01/00 0101 00 a b c d Testing of multiple faults by pairs of patterns b  1 11 Tested path for b  1/0 00/11 11/11 The lower path from b is under test A pair of patterns is applied on b There is a masking fault c  1 0101 c  1 1 st pattern: fault b  1 is masked Either the fault on the path is detected or the masking fault is detected No error Error 2 nd pattern: fault c  1 is detected The secret: 1st pattern tests b 2nd pattern tests c

19. Research in ATI © Raimund Ubar Avoiding Multiple Fault Masking x111x111 x210x210 T1 Fault masking T2 x311x311 T3 Fault is detected 19/29 Test x 11 x 21 x 12 x 31 x4x4 !x 13 x 22 x 32 YYFYF T10100111000 T21110101011 T31010100001 & & & 1 & x1x1 x2x2 x3x3 x4x4 y Multiple fault: x 11  1, x 21  0, x 31  1 x210x210 x311x311 x 11  1 The concept of Test Pair Test Pair Does not Work The concept of Test Group

20. Research in ATI © Raimund Ubar 20 11 00 c  1 a  0 L 1 (a=1) L M (a=0) L0L0 m0m0 Topological view on fault masking L 1 - Path under test L M - Masking path Test pair for a works Test generation topology Masking fault Node under test

21. Research in ATI © Raimund Ubar 21/29 Testing Multiple Faults with Test Pairs L 1 - Path under test L M - Masking path 11 00 c  1 a  0 L1L1 LMLM L0L0 m0m0 Test pair for {a} works well! Node c  1 KEEPS masking path active Test Pair Target 11 00 c  1 a 0 a 0 a L1L1 LMLM L0L0 L’ M m0m0 Test pair for {a} does not work! Node a desactivates the masking path

22. Research in ATI © Raimund Ubar 22/29 Test Group Concept The 3 rd test pattern for b restores the masking path 11 00 c  1 a 0 a 0 a L1L1 LMLM L0L0 L’ M m0m0 b Node a destroys the masking path Test group for {a, b} works Test group joins two test pairs Test Group Target abY 111 010 101

23. Technical University Tallinn, ESTONIA Critical Path Tracing & & 1 1 1 2 3 4 5 a c b 1 1 0 0 0 0 0 1 1 y 12 34 5 y Problems : & & 1 1 1 1/01/0 y & & 1 0 1 1 y 1/0 1 1 1 1 The critical path is not continuous The critical path breaks on the fan-out

24. Research in ATI © Raimund Ubar Combinational Fault diagnosis 0110 T 6 0010011 FaultF 5 located FaultsF 1 andF 4 are not distinguishable Fault localization by fault tables No match, diagnosis not possible

25. Research in ATI © Raimund Ubar Sequential Fault Diagnosis Sequential fault diagnosis by Edge-Pin Testing Diagnostic tree: Two faults F 1,F 4 remain indistinguishable Not all test patterns used in the fault table are needed Different faults need for identifying test sequences with different lengths The shortest test contains two patterns, the longest four patterns

26. Research in ATI © Raimund Ubar 26 Properties of SSBDDs Property 2: If a test vector X activates in SSBDD a 0-path (1-path) which travers a subset of nodes M, then only 0-nodes (1-nodes) have to be considered as fault candidates Speeding-up simulation: M = {1,2,3,4,6,7} M* = {1,6,7} – by Property 2 M** = {6,7} – by Property 1 Fault diagnosis and fault simulation can be speed-up by using Property 2 Only 6 and 7 have to be considered Fault diagnosis / Fault simulation: y y Sequential fault diagnosis by signal pinpointing

27. Research in ATI © Raimund Ubar Test Generation on Binary DDs and High Level DDs m y 1 0 m Y 1 0 2 h FkFk FnFn lmlm l1l1 l0l0 l0l0 l1l1 l2l2 lhlh lklk l k+1 F k+1 lnln lmlm GyGy GYGY Binary DD with 2 terminal nodes and 2 outputs from each node General case of DD with n  1 terminal nodes and n  1 outputs from each node

28. Research in ATI © Raimund Ubar High Level Decision Diagrams and System Testing RTL-statement: Terminal nodes RTL-statement faults: data storage, data transfer, data manipulation faults Nonterminal nodes RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding, control faults K: (If T,C) R D  F(R S1,R S2,…R Sm ),  N 28 Control path Data path

29. Technical University Tallinn, ESTONIA Test Generation for Digital Systems y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Multiple paths activation in a single DD Control function y 3 is tested Data path Decision Diagram High-level test generation with DDs: Conformity test Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 2  IN  R 1  R 1 * R 2 Test program:

30. Technical University Tallinn, ESTONIA Test Generation for Digital Systems High-level test generation with DDs: Conformity test Test template: Test program: For D = 0,1,2,3 Begin Load R1 = IN1 Load R2 = IN2 Apply IN = IN3 y 1 y 2 y 3 y 4 = 00D2 Read R2 End R2(D) Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 2  IN  R 1  R 1 * R 2

31. Technical University Tallinn, ESTONIA Test Generation for Digital Systems y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Single path activation in a single DD Data function R 1 * R 2 is tested Data path Decision Diagram High-level test generation with DDs: Scanning test Control: y 1 y 2 y 3 y 4 = 0032 Data: For all specified pairs of (R 1, R 2 ) Test program:

32. Technical University Tallinn, ESTONIA Scan-Path for Making Systems Transparent Hierarhical test generation with Scan-Path: Bus Scan-Out

33. Technical University Tallinn, ESTONIA Functional Synthesis of High-Level DDs Data-Flow Diagram High-Level DDs can be synthesized by symbolic execution of the Data-Flow Diagram F2

34. Technical University Tallinn, ESTONIA Synthesis of High-Level DDs High-Level DDs can be synthesized by symbolic execution of the Data-Flow Diagram: F2AXAC AX AC=0 PC PC+1 Decision Diagrams: F0AC AC+1 F2 AC AX F1 1 1 0 0 01

35. Research in ATI © Raimund Ubar 35 A B C M ADR MUX 1 2 ALU COND Control Path Data Path  / FF y x q q z z 1 z 2 Digital system Data Flow Diagram q=0 q=1 q=4 q=2 q=3 q=5 Synthesis of HLDDs for Digital Systems

36. Research in ATI © Raimund Ubar Synthesis of Functional HLDDs Data Flow Diagram/FSMD Begin A = B + C x A A =  A + 1 B = B + C x A B =  BC =  C x B  C x C A = A +  B + C x C C = A + B A =  C + B END 0 0 0 0 0 1 1 1 1 1 Constraints Assignment statements qxAxA xBxB xCxC 0 A = B + C; q = 1 10 A = A + 1; q = 4 11 B = B + C; q = 2 20 C = A + B; q = 5 21 C = C; q = 3 30 C = A + B; q = 5 31 A = C + B; q = 5 40 B = B 400 A = A + B + C; q = 5 401 q = 5 41 C = C; q = 5 Results of cycle based symbolic simulation: q = 0 q = 1 q = 2 q = 3 q = 4 q = 5

37. Research in ATI © Raimund Ubar Synthesis of HLDDs Constraints Assignment statements qxAxA xBxB xCxC 0 A = B + C; q = 1 10 A = A + 1; q = 4 11 B = B + C; q = 2 20 C = A + B; q = 5 21 C = C; q = 3 30 C = A + B; q = 5 31 A = C + B; q = 5 40 B = B 400 A = A + B + C; q = 5 401 q = 5 41 C = C; q = 5 Results of symbolic simulation: qxAxA xBxB xCxC A 0B + C 10 A + 1 31 C + B 400 A + B + C Extraction of the behaviour for A: A = f (q, A, B, C, x A, x C ) = = (q=0)(B+C)  (q=1)(x A =0) (  A + 1)  (q=3)(x C =1)(  C+B)  (q=4)(x A =0)(x C =0)(A+  B + C + 1) Predicate equation for A:

38. Research in ATI © Raimund Ubar Synthesis of HLDDs qxAxA xBxB xCxC A 0B + C 10 A + 1 31 C + B 400 A + B + C Extraction of the behaviour for A: A = (q=0)(B+C)  (q=1)(x A =0) (  A + 1)  (q=3)(x C =1)(  C+B)  (q=4)(x A =0)(x C =0)(A+  B + C + 1) Predicate equation for A: Decision diagram for A: Synthesis method: similar to Shannon’s expansion theorem:

39. Research in ATI © Raimund Ubar HLDD Model for Testing a System Described by DFG Data Flow Diagram Decision Diagrams Register variables State variable

40. Research in ATI © Raimund Ubar 40 System with 4 HLDDsVector HLDD High-Level Vector Decision Diagrams

41. Research in ATI © Raimund Ubar 41 System with 4 HLDDsVector HLDD High-Level Vector Decision Diagrams

42. Technical University Tallinn, ESTONIA Test Generation for Microprocessors I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  IA I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A Test program generation for a microprocessor (example): Instruction set: IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor:

43. Technical University Tallinn, ESTONIA Decision Diagrams for Microprocessors High-Level DD-based structure of the microprocessor (example): DD-model of the microprocessor: OUT R A IN I IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 A + R

44. Technical University Tallinn, ESTONIA Test Program Synthesis for Microprocessors DD-model of the microprocessor: Scanning test program for adder: Instruction sequence T = I 5 (R)I 1 (A)I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10

45. Research in ATI © Raimund Ubar 45 OPBSemanticRT level operations 0 0READ memoryR(A1) = M(A)PC = PC + 2 1WRITE memoryM(A) = R(A2)PC = PC + 2 1 0TransferR(A1) = R(A2)PC = PC + 1 1Complement R(A1) =  R(A2) PC = PC + 1 2 0AdditionR(A1) = R(A1)+ R(A2)PC = PC + 1 1SubtractionR(A1) = R(A1)- R(A2)PC = PC + 1 3 0JumpPC = A 1Conditional jumpIF C=1, THEN PC = A,ELSE PC = PC + 2 From MP Instruction Set to HLDDs OP B 0 M(A) 1 R(A2) M(A) 0 1-3 OP 0 PC 1, 2 B 3 A 0 PC + 2 PC + 1 C 1 0 1 A1 R0R0 0 R(A1) R1R1 1 R2R2 2 R3R3 3 A2 R0R0 0 R(A2) R1R1 1 R2R2 2 R3R3 3 A1 = 0 R0R0 R0R0 0 1 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 OP B0B0 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B2 2 1 0 R(A1) - R(A2) 3 R(A1) R(A1) + R(A2) R(A1) Instruction code: ADD A1 A2 R 3 = R 3 + R 2 PC = PC+1 OP=2. B=0. A1=3. A2=2

46. Research in ATI © Raimund Ubar 46 HLDDs for MP InstrSet A1 = 0 R0R0 R0R0 0 OP B0B0 1 0 M(A) 1 0 B1B1 1 R(A2) 1 0 B2B2 2 1 0 R(A1) - R(A2) 3 A1 = 3 R3R3 R3R3 0 1 R 1, R 2 R(A1) R(A1) + R(A2) R(A1) Registers and ALU A1 R0R0 0 R(A1) R1R1 1 R2R2 2 R3R3 3 A2 R0R0 0 R(A2) R1R1 1 R2R2 2 R3R3 3 Register Decoding OP 0 PC 1, 2 B 3 A 0 PC + 2 PC + 1 C 1 0 1 Program Counter OP B 0 M(A) 1 R(A2) M(A) 0 1-3 Memory Access Instruction code: ADD A1 A2 OP=2. B=0. A1=3. A2=2 R 3 = R 3 + R 2 PC = PC+1

47. Research in ATI © Raimund Ubar 47 OPOP LDA0AC=M AND1 AC=AC  M ADD2 AC=AC  M SUB3 AC=AC  M JMP4PC=A STA5M=AC JSR6 PC=A Jump to subroutine Parwan: Instruction Set OPIP CLA701AC=0 CMA702 AC=  AC CMC704 C=  C ASL708AC=2AC ASR709AC=AC/2 BRA_N710If negative BRA_Z712If zero BRA_C714If carry BRA_V718If overflow

48. Research in ATI © Raimund Ubar PC_A P1P1 OP 1 A1A1 PC_A + 2 P2P2 N A2A2 I 0 1 0 4,6 0-3, 5 7 7 OP 3 1 0 PC_A + 1 OP 2 7 PC_A 6 Z C V PC_A + 2 2 4 8 0 0 0 0 1 1 1 Next PC offset calculation Instruction addressing OP. I. P LOC(PC_A ) 0-255 0-15 PC_P PC_A A LOC(PC_A+1 ) 0-255 0-15 PC_P PC_A PC_P OP 1 P1P1 4 PC_P Next memory page calculation ALU Flags OP N I 0 - 3 0 7 N F N (AC,M’) P 2,8,9 F c2 (AC) C V OP C I 2,3 0 7 F c1 (AC,M’) P 4,8 F c2 (AC) OP V I 2,3 0 7 F v1 (AC,M’) P 8 F v2 (AC) OP Z I 0 - 3 0 7 Z F z (AC,M’) P 2,8,9 F c2 (AC) Output behaviour M’ (A) OP 5 AC M’ P A LOC(A ) 0-255 0-15 Direct addressing LOC(M’) P M’’ M’ 0-15 Indirect addressing ALU Data Path AC P1P1 OP 1 M’ AC & M’ AC + M’ AC - M’ AC P3P3 00 I OP 3 0 1 M’’ 0 0 0 1 2 3 7 OP 2 1 AC AC/2 2 8 9  AC 2AC 4  AC Parwan: HLDD Model