1. Laura Gonella – University of Bonn – 27/09/20111 The Shunt-LDO regulator for powering the upgraded ATLAS pixel detector Laura Gonella University of Bonn TWEPP, Vienna, 27/09/2011

2. Laura Gonella – University of Bonn – 27/09/20112 ATLAS pixel detector upgrades Insertable B Layer - IBL (2013) –Insertion of a 4 th pixel layer inside current pixel detector –Only approved upgrade project so far Possible future upgrades –Phase-1 upgrade (>2017) Replace the current pixel detector, keep the IBL –HL-LHC upgrade (>2020) If Phase-1 upgrade: replace the IBL, keep the new pixel detector If no Phase-1 upgrade: replace the pixel detector and IBL IBL on new beam pipe Existing B-layer IBL New pixel detector Phase-1 (tentative layout)

3. Laura Gonella – University of Bonn – 27/09/20113 Powering schemes for upgrades Requirements: –Reduce the volume of LV services in the active area –Reach higher power efficiency (power efficiency of the present ATLAS pixel detector = 20%)  Direct powering is NOT an option for the upgrades of the ATLAS pixel detector IBL –Extra requirement: Backwards compatibility with existing counting room supplies and PP2 regulators –Direct powering with on-chip linear regulators Allow for higher V drop and thus smaller cables Reduce cables volume without changing the current that must be supplied Phase-1 and HL-LHC –2 powering schemes under consideration to reduce the amount of transmitted current wrt the direct powering scheme Serial powering Direct powering with on-chip DC-DC converters

4. Laura Gonella – University of Bonn – 27/09/20114 FE-I4 powering Powering blocks in FE-I4A –No hard-wired power option –2 Shunt-LDO regulators –1 switched capacitor DC-DC converter  Allows testing all powering options for upgrades New pixel FE chip for ATLAS pixels upgrades: FE-I4 –FE-I4A: full scale prototype, available since 11/2010 –FE-I4B: production chip for IBL, submitted 16/09/2011 FE-I4 power specs: –VDDA = 1.5V –VDDD = 1.2V –I = 0.490 – 0.560A Analog I = 0.350 – 0.380A Digital I = 0.140 – 0.180A

5. Laura Gonella – University of Bonn – 27/09/20115 Shunt-LDO regulator in FE-I4A Specs –REG_IN = 1.4 – 2.5V / 0.5 – 0.6A –REG_OUT = 1.2 – 1.5V –VDD Shunt = 1.4 – 2.5V –V ref = 0.6 – 0.75 V Reg1 input connected to DC-DC output I bias generated internally V ref has to be provided externally R3 can be internal (R int = 2KΩ) or external (R ext ) Selectable working mode by external wire bonds –Shunt-LDO mode or LDO mode LDOShunt-LDO with R int Shunt-LDO with R ext Reg2Reg1 & DC-DC

6. Laura Gonella – University of Bonn – 27/09/20116 Shunt-LDO mode Dedicated serial powering mode It combines two regulation loops –Shunt regulation circuitry  const I load –LDO (Low Drop Out) regulation loop  const V out Shunt regulator LDO The regulator works as an improved shunt –Safe parallel operation –Parallel operation of regulators with different V out possible –Capability of shunting the total I in current (0.6A) The pass transistor of the LDO becomes the R slope of the shunt R slope Shunt 

7. Laura Gonella – University of Bonn – 27/09/20117 Voltage generation Settings: –V ref = 0.750V –R3 = 2KΩ Vout (*) reaches the selected value after saturation of the regulator V out = 2 x V ref = 1.5V ΔV out / ΔI in = 1mV / 50mA R in = V in / I in = ~3 – 5Ω for I in = 0.310 – 0.600A – In agreement with simulations For I in = 0.140 – 0.300A oscillations observed for V in and V out, V out is not regulated (*) All voltages are measured at the pad. V out is corrected for the effective V ref shift due to the V drop on the gnd lines between chip ground and board ground. V in is corrected for the ground difference as well. V in V out

8. Laura Gonella – University of Bonn – 27/09/20118 Oscillation and stability This behavior was not observed in simulation or with the prototypes –Different error amplifier and biasing circuit wrt prototypes Possible reasons –Compensation loops –Gain of the error amplifier –Biasing current This issue needs to be better understood with simulations and further measurements @Iin = 0.280A: ΔV out = ~0.360V, f = ~1MHz V out = 1.5V, I in = 0.280A V compensation loop External filter: C out = 2.2μf, ESR = 1Ω I compensation loop Internal filter

9. Laura Gonella – University of Bonn – 27/09/20119 Load regulation Settings –V ref = 0.750V –R3 = 2KΩ – I in = 0.600A – External I load = 0 – 0.600A V out is stable until I in – I load < min I shunt Min I shunt = 5mA!!! R out = V out / V in = 0.150Ω –This value is higher than expected –Gain of the error amplifier –R out of the pass transistor –Needs more investigations with simulations IR I in I load I shunt

10. Laura Gonella – University of Bonn – 27/09/201110 Power efficiency Sources of inefficiency for single device –V drop = V in - V out –I shunt = I in - I load Tuning the value of R3 allows to minimize I shunt and V drop –Min I shunt = 0.005A –Min V drop = 0.100V Example: V out = 1.5V and I load = 0.300A –V ref = 0.750V –R3 = 2KΩ: Vin = 1.6V @ I in = 0.310A –Power efficiency = 90% –This depends strongly on the stability of the load

11. Laura Gonella – University of Bonn – 27/09/201111 Shunt-LDO mode for FE-I4 2 Shunt-LDO regulators needed to provide VDDA and VDDD Parallel operation, i.e same I in and gnd Different R3 to optimize I shunt –I load_a = 0.350 – 0.380A –I load_d = 0.140 – 0.180A Settings – Conservative option: –I in = 0.600A I a = 0.400A, I d = 0.200A –V in = 1.6V –R3 = 2KΩ for the analog Shunt-LDO –R3 = 5KΩ for the digital Shunt-LDO –V ref analog = 0.750V, V ref digital = 0.600V Analog Shunt-LDO Digital Shunt-LDO I in gnd VDDA VDDD IaIa IdId I load_a I load_d

12. Laura Gonella – University of Bonn – 27/09/201112 2 Shunt-LDO in parallel I in splitting –Improved shunt: 2 Shunt-LDO regulators can be operated in parallel with different shunt current –At I in = 0.600A, I a = 0.396A, I d = 0.204A Voltage generation –Both outputs are regulated for I in > 0.460A –Oscillations observed for I in = 0.190 – 0.450A IaIa V in_a, V in_d IdId V out_a, V out_d

13. Laura Gonella – University of Bonn – 27/09/201113 Shunt-LDO mode for FE-I4: power efficiency Sources of inefficiency for 2 Shunt-LDO regulators connected in parallel generating different output voltages –V drop = V in - V out –I shunt = I in - I load – ΔV = VDDA – VDDD I in = 0.6AI in = 0.55AI in = 0.49A Nominal current High current Low current Nominal current Optimized I shunt Low current Optimized I shunt VDDA [V] 1.4441.4431.4491.4481.453 VDDD [V] 1.1831.1781.1881.1821.188 I load_a [A] 0.350.380.30.350.3 I load_d [A] 0.140.180.10.140.1 I load_tot [A] 0.490.560.40.490.4 V drop [V] 0.2120.2140.2040.1640.112 ΔV [V] 0.2610.2650.2610.2660.265 I shunt_a [A] 0.0460.0160.0950.0070.010 I shunt_d [A] 0.0630.0230.1030.0520.080 P eff 68%77%56%76%72% Optimized P eff for 2 Shunt-LDO regulators powering FE-I4: 70 – 80%

14. Laura Gonella – University of Bonn – 27/09/201114 LDO mode Shunt circuitry is switched off by grounding R int, R ext and VDD Shunt The device behaves as a standard LDO regulator Working mode considered for IBL –A 3 rd working mode, partial shunt mode, is also considered for IBL (see back-up slides) Voltage generation for I load = 0.200A and 0.600A –V out < 2xV ref due to the R out –No oscillations observed in this mode Load regulation for different V drop –V drop –0.100V for V out = 1.5V –0.200V for V out = 1.2V –R out = 0.150Ω I load = 0.2A I load = 0.6A I quiesc = 1mA

15. Laura Gonella – University of Bonn – 27/09/201115 FE-I4 powering with the Shunt-LDO LDO mode (and partial shunt mode) –Common V in = 1.8V to account for transients on the V in lines (see back-up slides) –ESR of output capacitor 1Ω is not needed for this mode No difference between 1Ω and 0Ω – C in = 10μf: value given by system simulation Shunt-LDO mode –ESR not removed to minimize oscillation – C in = 2.2μf: value given by Shunt-LDO simulations 2μf2μf 1Ω1Ω Reg2 Reg1 0.6A 2.2μf VDDA VDDD_T3 VDDD VDDefuse VDD_PLL 2μf2μf 1Ω1Ω Reg2 Reg1 1.8V 10μf VDDA VDDD_T3 VDDD VDDefuse VDD_PLL 2μf2μf 2μf2μf

16. Laura Gonella – University of Bonn – 27/09/201116 FE-I4 noise FE-I4 powered without regulators and with regulators in the different modes –Bare chip, untuned Power supply: Keithley sourcemeter No problem configuring the chip and running threshold scan No significant increase of noise Note: for Shunt-LDO mode I in = 0.700A –Oscillation lasts until I in = 0.680A –Only 1 chip tested so far. Not possible yet to conclude if increased range of oscillation is due to the FE-I4 being the load DirectShunt-LDO modeLDO modePartial shunt mode Threshold (e)4611447044894475 Threshold dispersion (e) 652.1570.6619.1614.7 Noise (e)150.2159.6155.2156 Noise dispersion (e) 16.0113.1316.6716.01

17. Laura Gonella – University of Bonn – 27/09/201117 IBL powering dedicated test setup To test the IBL powering scheme a dedicated test setup using the ATLAS pixel detector power scheme was used –„PP2“ voltage regulator Voltage regulator placed 14m away from the pixel detector –„Type2“ cables Experiment cables with sense lines 9m long Measurements showed good compatibility between PP2 regulator and Shunt-LDO regulator No noise increase wrt direct powering LDO modePartial shunt mode Threshold (e)44264429 Threshold dispersion (e) 613613.5 Noise (e)154155.2 Noise dispersion (e) 16.4316.8

18. Laura Gonella – University of Bonn – 27/09/201118 Shunt-LDO regulator in FE-I4B The core regulator design has not been modified The V ref is integrated –Use I ref (2μA) with external resistor –Two replica of the I ref –I ref powered by analog Shunt-LDO + startup circuit –Two bias DACs used to trim down the two V ref R int = 8KΩ and 16KΩ resp. for the analog and digital Shunt-LDO for operation in partial shunt mode R int pad removed, R int connected to VDD Shunt R ext pad kept to allow for Shunt-LDO mode operation with different R3 VDDShunt

19. Laura Gonella – University of Bonn – 27/09/201119 Conclusions and outlook The Shunt-LDO regulator in FE-I4 shows good performance However, some issues need to better understood and corrected for the next version –In Shunt-LDO mode: oscillations in a certain range of I in –In all modes: R out value FE-I4 has been powered without problems with the regulator in all modes –No significant noise increase observed IBL powering –Tests have been successfully completed with a dedicated test setup using power services element of the ATLAS pixel detector Serial powering for future upgrades –Tests will continue on modules –A serial powering demonstrator will be built with FE-I4A –More sophisticated prototyping with FE-I4B

20. Laura Gonella – University of Bonn – 27/09/201120 Partial shunt mode The regulator is connected in Shunt-LDO mode but powered as an LDO Benefit: Fixing a minimum current flowing to the regulator allows to reduce transiens at the input This working mode is underconsideration for the IBL Transients are reduced in partial shunt mode as expected –Transients on V out are due to V in falling under the minimum required for regulation –Higher V in reduces transients on V out The level shift on the V out due to R out, on the V in is due to the V drop on the PCB traces and wire bonds Iload VinA VoutA Partial shunt modeLDO mode V in = 1.8V, V out = 1.5V ΔI load –external –0.3A –measured across R = 0.1Ω

21. Laura Gonella – University of Bonn – 27/09/201121 LDO mode Single device power efficiencyLine regulation = ΔV out / ΔV in Vout (V)Iload = 0.2AIload = 0.6A 1.5V0.00 1/ 0.3750.001 / 0.072 1.2V0.001 / 0.50.001 / 0.070