1. ACOE2011 Cache memory Homework – Q1 A computer has a 32 bit address and a 64 bit data bus with address resolution to the byte level. The computer is using a direct mapped cache with 4K cache lines. The size of each cache line is 64 bytes. a)What is the size of the cache? b)How many bits are there in the line, the index and the tag fields? c)What is the size of the tag memory? d)How many memory cycles are required to fill up a cache line? Data Solution Tag 64 bytes per line TagIndexLine 32-bit address bus 4K Cache lines

2. ACOE2012 Cache memory Homework – Q1 a)What is the size of the cache? Cache size = 4K lines X 64 bytes/line = 4K X 64 = 256Kbytes b)How many bits are there in the line, the index and the tag fields? Line bits: 2 L = 64 = 2 6  Number of line bits = 6 Index bits: 2 N = 4K = 2 2 X 2 10 = 2 12  Number of index bits = 12 Number of tag bits = Size of address bus - Number of line bits - Number of index bits = 32 – 6 – 12 = 14 bits c)What is the size of the tag memory? Size of tag memory = Number of cache lines X Number of tag bits = 4K x 14 bits d)How many memory cycles are required to fill up a cache line? Number of memory cycles = Size of cache line / Size of data bus (in bytes) = 64 / (64/8) = 64 / 8 = 8 cycles

3. ACOE2013 Cache memory Homework – Q2 A computer has a 32-bit address bus with a direct mapped cache, using 4 line bits, 16 tag bits and 12 index bits. a)Specify i.The cache block size ii.The size of the cache iii.The size of the tag memory b)Specify whether the following address pairs can be placed in the cache simultaneously. i. 3AC6F456 and 26A35456 ii. 3F08C304 and 3F08C371 iii. 5E3C7680 and 8F3C768A iv. 22334455 and 2233445C Data Solution Tag 4 bits TagIndexLine 32-bit address bus 12 bits

4. ACOE2014 Cache memory Homework – Q2 a.i) Number of blocks = 2 (number of index bits) = 2 12 = 2 2 x 2 10 = 4K Size of the cache = Number of blocks x Block size = 4K x 16 = 64Kbytes a.ii)Block size = 2 (number of line bits) = 2 4 = 16 bytes a.iii) Size of the tag memory = Number of blocks x Number of tag bits = 4K x 16 bits b) Specify whether the following address pairs can be placed in the cache simultaneously. Address Answer Yes/No Justification TagIndexLine i 3AC6F456 YesDifferent index 26A35456 ii 3F08C304 YesDifferent index 3F08C371 iii 5E3C7680 NoSame index and different tag 8F3C768A iv 22334455 YesSame index and same tag, i.e same cache block 2233445C