1. Saverio MINUTOLITOTEM Trigger Meeting 12 January 20091 ~6k wires VFAT2 CSC T1 ARM 1 8 x2 1 30 ~6k wires VFAT2 CSC T1 ARM 1 8 x2 1 x2x15 30 T1 TRG_TOTFED 12 33 T1 TRG_TOTFED 12 33 LONEG VFAT 8bit 32 COUNTING ROOM CAVERN Trigger Bits 2 x 480 = 960 (16) x2x15 x8 VFAT 8bit LV1 16 T1TRIME T1 TRIME : 32 trigger bits 12 bunch counter bits 40Mhz clock T1 trigger architecture

2. Saverio MINUTOLITOTEM Trigger Meeting 12 January 20092 Preliminary considerations  Problem: –needs to merge the trigger bits sent from one telescope in the same FPGA  Host board can’t do this but, it provides all the trigger bits shared on several connectors.  Solution: –Add to the Host board the TRIME piggy back mezzanine. –TRIME collects all the trigger bits within the same FPGA, generates trigger primitives information coded within 32 bits and send them to the LONEG board.  Warning: –Mechanical constraints, needs to fit 16 smd (64 pin) connectors. –Insertion and extraction tool needed.

3. Saverio MINUTOLITOTEM Trigger Meeting 12 January 20093 TOTFED I/O Interfaces S-Link64 13bits Reserved 3bits MAIN1 TTCrx, Clk.. 20bits 6bits TRIME receives:  TTCrx bits, JTAG, clock, Reset, L1A from J8  Trigger bits from: –J9, J10, J11, J12 (ORx1) –J14, J15, J16, J17 (ORx2) –J19, J20, J21, J22 (ORx3)  Private 32 bits bus: –J8 from Main 1 –J13 from Main 2 –J18 from Main 3  Local Bus: – Add:32b, Data:20b, Ctrl:6b –From J44  Power: –Reg. P2V5 from J10, J15, J20 –VME P3V3 from J11, J16, J21 –VME +5V from J12, J17, J22 –VME P12V from J44

4. Saverio MINUTOLITOTEM Trigger Meeting 12 January 20094  Firmware functionalities –Mask noisy channels –Trigger bits stretching –Trigger algorithm remote selection –Multiplicity counters –Remote parameter selection  Other –Debugging USB port –Flash memory –… TRIME main functionalities

5. Saverio MINUTOLITOTEM Trigger Meeting 12 January 20095 Host board blocks Main 1 Main 2 Main 3 Merger VME mFEC TTS VME S-Link 64 Opto Rx1 Opto Rx2 Opto Rx3 Local Bus Local Bus TTCrx- QPLL 12 x16 GOH chs. 32 bits M1 bus TTCrx, JTAG Clock, LV1 Reset, Serial_b 12 x16 GOH chs. 32 bits M2 bus 12 x16 GOH chs. 32 bits M3 bus

6. Saverio MINUTOLITOTEM Trigger Meeting 12 January 20096 T1 TRIgger MEzzanine(1)  T1 TRG_TOTFED Trigger FPGA OptoRx1 OptoRx3 OptoRx2 2 x 50 wires flat cable Local Bus 32 trigger bits BC + clock TRIME LONEG

7. Saverio MINUTOLITOTEM Trigger Meeting 12 January 20097 Trigger FPGA OptoRx1 OptoRx3 OptoRx2 LONEG Local Bus 32 trigger bits BC + clock TOP BOTTOM TRIME with I/O connectors on front panel. TRIME T1 TRIgger MEzzanine(2)  T1 TRG_TOTFED

8. Saverio MINUTOLITOTEM Trigger Meeting 12 January 20098 TRIME  LONEG connections T1 TRIME I/O : 32 trigger bits 12 bunch counter bits 40Mhz clock N.T. Not used pins will be connected as TRIME inputs. + 5 LVDS general purpose inputs. S.M.