1. Computer Science and Engineering Copyright by Hesham El-Rewini Advanced Computer Architecture CSE 8383 January 19 2006 Session 2

2. Computer Science and Engineering Copyright by Hesham El-Rewini Contents (Memory)  Memory Hierarchy  Cache Memory  Placement Policies n Direct Mapping n Fully Associative n Set Associative  Replacement Policies

3. Computer Science and Engineering Copyright by Hesham El-Rewini Memory Hierarchy CPU Registers Cache Main Memory Secondary Storage Latency Bandwidth Speed Cost per bit

4. Computer Science and Engineering Copyright by Hesham El-Rewini Sequence of events 1.Processor makes a request for X 2.X is sought in the cache 3.If it exists  hit (hit ratio h) 4.Otherwise  miss (miss ratio m = 1-h) 5.If miss  X is sought in main memory 6.It can be generalized to more levels

5. Computer Science and Engineering Copyright by Hesham El-Rewini Cache Memory  The idea is to keep the information expected to be used more frequently in the cache.  Locality of Reference n Temporal Locality n Spatial Locality  Placement Policies  Replacement Policies

6. Computer Science and Engineering Copyright by Hesham El-Rewini Placement Policies How to Map memory blocks (lines) to Cache block frames (line frames) Blocks (lines) Block Frames (Line Frames) Memory Cache

7. Computer Science and Engineering Copyright by Hesham El-Rewini Placement Policies n Direct Mapping n Fully Associative n Set Associative

8. Computer Science and Engineering Copyright by Hesham El-Rewini Direct Mapping  Simplest  A memory block is mapped to a fixed cache block frame (many to one mapping)  J = I mod N n J  Cache block frame number n I  Memory block number n N  number of cache block frames

9. Computer Science and Engineering Copyright by Hesham El-Rewini Address Format  Memory  M blocks  Block size  B words  Cache  N blocks  Address size log 2 (M * B) TagBlock frameWord log 2 Blog 2 NRemaining bits log 2 M/N

10. Computer Science and Engineering Copyright by Hesham El-Rewini Example  Memory  4K blocks  Block size  16 words  Address size log 2 (4K * 16) = 16  Cache  128 blocks TagBlock frameWord 475

11. Computer Science and Engineering Copyright by Hesham El-Rewini Example (cont.) 128 129 255 0 1 127 3968 4095 0 1 2 127 MemoryTagcache 0131 5 bits

12. Computer Science and Engineering Copyright by Hesham El-Rewini Fully Associative  Most flexible  A memory block is mapped to any available cache block frame  (many to many mapping)  Associative Search

13. Computer Science and Engineering Copyright by Hesham El-Rewini Address Format  Memory  M blocks  Block size  B words  Cache  N blocks  Address size log 2 (M * B) TagWord log 2 BRemaining bits log 2 M

14. Computer Science and Engineering Copyright by Hesham El-Rewini Example  Memory  4K blocks  Block size  16 words  Address size log 2 (4K * 16) = 16  Cache  128 blocks TagWord 412

15. Computer Science and Engineering Copyright by Hesham El-Rewini Example (cont.) 0 1 4094 4095 0 1 2 127 Memory Tagcache 12 bits

16. Computer Science and Engineering Copyright by Hesham El-Rewini Set Associative  Compromise between the other two  Cache  number of sets  Set  number of blocks  A memory block is mapped to any available cache block frame within a specific set  Associative Search within a set

17. Computer Science and Engineering Copyright by Hesham El-Rewini Address Format  Memory  M blocks  Block size  B words  Cache  N blocks  Number of sets S  N/num of blocks per set  Address size log 2 (M * B) log 2 B TagSetWord log 2 S Remaining bits log 2 M/S

18. Computer Science and Engineering Copyright by Hesham El-Rewini Example  Memory  4K blocks  Block size  16 words  Address size log 2 (4K * 16) = 16  Cache  128 blocks  Num of blocks per set = 4  Number of sets = 32 4 TagSetWord 57

19. Computer Science and Engineering Copyright by Hesham El-Rewini Example (cont.) 0 1 2 3 126 127 Set 0 Tag cache 7 bits Set 31 32 33 63 0 1 314095 Memory 01 127 124 125

20. Computer Science and Engineering Copyright by Hesham El-Rewini Comparison  Simplicity  Associative Search  Cache Utilization  Replacement

21. Computer Science and Engineering Copyright by Hesham El-Rewini Group Exercise The instruction set for your architecture has 40-bit addresses, with each addressable item being a byte. You elect to design a four-way set-associative cache with each of the four blocks in a set containing 64 bytes. Assume that you have 256 sets in the cache. Show the Format of the address

22. Computer Science and Engineering Copyright by Hesham El-Rewini Group Exercise (Cont.) Consider the following sequence of addresses. (All are hex numbers) 0E1B01AA05 0E1B01AA07 0E1B2FE305 0E1B4FFD8F 0E1B01AA0E In your cache, what will be the tags in the sets(s) that contain these references at the end of the sequence? Assume that the cache is initially flushed (empty).

23. Computer Science and Engineering Copyright by Hesham El-Rewini Replacement Techniques  FIFO  LRU  MRU  Random  Optimal