1. Massachusetts Institute of Technology Laboratory for Electromagnetic and Electronic Systems Group Meeting July 21, 2009 Justin Burkhart

2. Presentation Outline More Exact Analysis of Class E Resonant Boost Converter Gate Drive Options Transistor Layout Optimization

3. Boost Converter Operation Switch is opened and closed periodically The rectifier LC tank is assumed to have high Q such that the current in L 2 is purely sinusoidal L 1 and C 1 are tuned such that when the switch is opened, the voltage across the switch will ring back to zero half of a period later

4. Delivery of Power Inverter (lossless) Rectifier (lossless) + - + - V in V out P in P inv P out P in = P inv = P out

5. Delivery of Power Inverter (lossless) Rectifier (lossless) + - + - I in-dc +I 1 sin(wt)+I 2 sin(2wt)+… V in V out P in P inv P out P in = P inv = P out P in =V in I in-dc

6. Delivery of Power Inverter (lossless) Rectifier (lossless) + - + - I in-dc +I 1 sin(wt)+I 2 sin(2wt)+… I out-dc +I o1 sin(wt)+I o2 sin(2wt)+… V in V out P in P inv P out P in = P inv = P out P in =V in I in-dc P out =V out I out-dc

7. Delivery of Power Inverter (lossless) Rectifier (lossless) + - + - I in-dc +I 1 sin(wt)+I 2 sin(2wt)+… I inv-dc +I 1-inv sin(wt) V in V out P in P inv P out P in = P inv = P out P in =V in I in-dc P out =V out I out-dc P inv =P AC +P DC I out-dc +I o1 sin(wt)+I o2 sin(2wt)+…

8. Inverter: Detailed Analysis Unknowns: w o, z o, I AC, o 1, I L (0) Constraints: = P out /V in, = V IN, = 0, 0.5 V C-Fund I AC cos(o-o 1 ) = P out (1-V in /V out ) Known Initial Conditions: V c (0)=0 w o,z o

9. Inverter: Detailed Analysis Unknowns: w o, z o, I AC, o 1, I L (0) Constraints: = P out /V in, = V IN, = 0, 0.5 V C-Fund I AC cos(o-o 1 ) = P out (1-V in /V out ) Known Initial Conditions: V c (0)=0 Solve system of non-linear equations for each value of w o w o,z o

10. Rectifier: Detailed Analysis Unknowns: w r, z r, t on, t off Constraints: = V IN, = P OUT /V OUT, I AC and o 1 are constrained by the inverter Known Initial Conditions: V D (t off ) = V OUT, I L (t off ) = 0

11. Rectifier: Detailed Analysis Unknowns: w r, z r, t on, t off Constraints: = V IN, = P OUT /V OUT, I AC and o 1 are constrained by the inverter Known Initial Conditions: V D (t off ) = V OUT, I L (t off ) = 0 Solve system of non-linear equations

12. Gate Drive Options Hard Switched Gate Drive Loss arises from charging and discharging C ISS through a resistor every cycle. Thus, loss is proportional to switching frequency. Since the converter is operating at 75 MHz this loss can be substantial, however, this scheme has very low complexity. Resonant Gate Drive An inductor can be added in series with the gate to form a resonant circuit with C ISS. This essentially charges and discharges C ISS with a sinusoidal current. Loss occurs in R ISS.

13. Introduction to TI’s LBC5 Process Removed

14. LDMOS Layout Removed

15. LDMOS Layout Optimization Large LDMOS transistors are formed by connecting many smaller transistors in parallel Optimization serves to find the total device size, finger size, finger layout, and metal layout that achieves the highest converter efficiency Loss Model:

16. Scaling of Parasitics Removed

17. Optimization Procedure Sweep total device width Sweep number of fingers Calculate loss Choose total device width and number of fingers Find best aspect ratio and top metal layer layout

18. Solid Lines: Ross set by scaling measured data Dashed Lines: Ross set as 3 Rds Optimization Result (Hard Switched)

19. Solid Lines: Ross set by scaling measured data Dashed Lines: Ross set as 3 Rds Choose 45000um and 100 Fingers

20. Optimization Result (Resonant Gating) Solid Lines: Hard Switched Dashed Lines: Resonant Gating

21. Choose Aspect Ratio Total Area Available: 1500x1000 um Finger Cross Section: 13.8 um Finger Width: 245 um # of RowsTotal Length (um)Total Width (um) 11380245 2690490 3460735 4345980

22. Choose Aspect Ratio Total Area Available: 1500x1000 um Finger Cross Section: 13.8 um Finger Width: 245 um # of RowsTotal Length (um)Total Width (um) 11380245 2690490 3460735 4345980 3 rows is chosen

23. Top Metal Design

24. Metal 1 Gate

25. Top Metal Design Metal 1Metal 2 Source

26. Top Metal Design Metal 1 Drain Metal 2

27. Top Metal Design Metal 1Metal 2 SourceDrain

28. Taper Angle Optimization Adjust the size of the network based on the number of fingers per row and solve for equivalent resistance using MATLAB Node Matrix Voltage Vector Constant Vector

29. Taper Angle Optimization Optimization ignores metal resistance in connecting rows

30. Device Layout

31. Ideas for Improvement? Break long rows into multiple columns

32. Ideas for Improvement? Gate Metal 1Metal 2

33. Ideas for Improvement? Metal 1Metal 2

34. Ideas for Improvement? Metal 1Metal 2 Source