1. Chapter 6 FPGA Modules and Hardware Interface Design Professor Tzyy-Kuen Tien E-mail: tktien@mail.stut.edu.tw Http://www.eecs.stut.edu.twSTUT/EE

2. P-2/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 Outline 6.1 The Implementation of IDCT on FPGA 6.2 AMBA I/O Interface Design 6.3 I/O Interface Design

3. P-3/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.1 The Implementation of IDCT on FPGA 6.2 AMBA I/O Interface Design 6.3 I/O Interface Design

4. P-4/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.1 Compression/Decompression System  A block diagram of a compression/decompression system.  DCT/IDCT can be used in the system to reduce the bandwidth requirements.

5. P-5/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.1 Introduction to IDCT  Inverse Discrete Cosine Transform.  IDCT is used to decompress DCT compressed data in the decoder.  IDCT is one of the most computation-intensive parts of the MPEG decoding process.  A fast, hardware based IDCT implementation is crucial to speed the MPEG decoding process.

6. P-6/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.1 2D IDCT Equations (1/2)  The algorithm used for the calculation of the 2D IDCT coefficients is based on the following equation:  First, the 1D DCT of the rows are calculated and then the 1D IDCT of the columns are calculated. XC pq = ∑ ∑ XN mn · M-1N-1 m = 0n = 0 c(p)c(q) 4 ·cos Π(2m+1)p 2M ·cos Π(2n+1)q 2N (EQ 1)

7. P-7/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.1 2D IDCT Equations (2/2)  The 1D IDCT coefficients for the rows and columns can be calculated by separating equation 1 into the row part and the column part. C = K · cos (2·col number + 1) · row number ·Π 2 · M K = √1 N for row = 0, √2 K = N for row ≠ 0 C t = K · cos (2·row number + 1) · col number ·Π 2 · N K = √1 M for col = 0, K = √2 for col ≠ 0 M (EQ 2) (EQ 3) M = total number of columns, N = total number of rows.

8. P-8/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.1 Constant Values of C and C t  The constant values for C and C t calculated from equations 2 and 3 are as follows: 23170 23170 23170 23170 32138 27246 18205 6393 –6393 –18205 –27246 –32138 30274 12540 –12540 –30274 –30274 –12540 12540 30274 27246 –6393 –32138 –18205 18205 32138 6393 –27246 23170 –23170 –23170 23170 18205 –32138 6393 27246 –27246 –6393 32138 –18205 12540 –30274 30274 –12540 –12540 30274 –30274 12540 6393 –18205 27246 –32138 32138 –27246 18205 –6393 C = C t = 23170 32138 30274 27246 23170 18205 12540 6393 23170 27246 12540 –6393 –23170 –32138 –30274 –18205 23170 18205 –12540 –32138 –23170 6393 30274 27246 23170 6393 –30274 –18205 23170 27246 –12540 –32138 23170 –6393 –30274 18205 23170 –27246 –12540 32138 23170 –18205 –12540 32138 –23170 –6393 30274 –27246 23170 –27246 12540 6393 –23170 32138 –30274 18205 23170 –32138 30274 –27246 23170 –18205 12540 –6393

9. P-9/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.1 2D IDCT using Vector Processing  A one-dimensional 8-point IDCT followed by an internal double buffer memory, followed by another one-dimensional 8-point IDCT provides the 2D IDCT architecture.  Vector processing using parallel multipliers is a method used for implementation of IDCT.  Advantages of vector processing method. Regular structure, simple control and interconnect, good balance between performance and complexity of implementation. 1D IDCT RAM Double Buffer 1D IDCT

10. P-10/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.1 Behavioral Model (1/2)  The output Y of an 8 ‧ 8 IDCT for input X is given by Y = C ‧ X ‧ C t, where C is the cosine coefficients and C t is the transpose coefficients.  The equation can also be written as Y = C t ‧ Z, where Z = X ‧ C. X = x00 x01 x02 x03 x04 x05 x06 x07 x10 x11 x12 x13 x14 x15 x16 x17 x20 x21 x22 x23 x24 x25 x26 x27 x30 x31 x32 x33 x34 x35 x36 x37 x40 x41 x42 x43 x44 x45 x46 x47 x50 x51 x52 x53 x54 x55 x56 x57 x60 x61 x62 x63 x64 x65 x66 x67 x70 x71 x72 x73 x74 x75 x76 x77 C = 23170 23170 23170 23170 32138 27246 18205 6393 –6393 –18205 –27246 –32138 30274 12540 –12540 –30274 –30274 –12540 12540 30274 27246 –6393 –32138 –18205 18205 32138 6393 –27246 23170 –23170 –23170 23170 18205 –32138 6393 27246 –27246 –6393 32138 –18205 12540 –30274 30274 –12540 –12540 30274 –30274 12540 6393 –18205 27246 –32138 32138 –27246 18205 –6393

11. P-11/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.1 Behavioral Model (2/2) Z(0,0) = 23170x00 + 32138x01 + 30274x02 + 27246x03 + 23170x04 + 18205x05 + 12540x06 + 6393x07 Z(0,1) = 23170x00 + 27246x01 + 12540x02 – 6393x03 – 23170x04 – 3213805 – 30274x06 – 18205x07 Z(0,2) = 23170x00 + 18205x01 – 12540x02 – 32138x03 – 23170x04 + 6393x05 + 30274x06 + 27246x07 Z(0,3) = 23170x00 + 6393x01 – 30274x02 – 18205x03 + 23170x04 + 27246x05 – 12540x06 – 3213807 Z(0,4) = 23170x00 – 6393x01 – 30274x02 + 18205x03 + 23170x04 – 27246x05 – 12540x06 + 32138x07 Z(0,5) = 23170x00 – 18205x01 – 12540x02 + 32138x03 – 23170x04 – 6393x05 + 30274x06 – 27246x07 Z(0,6) = 23170x00 – 27246x01 + 12540x02 + 6393x03 – 23170x04 + 32138x05 – 30274x06 + 18205x07 Z(0,7) = 23170x00 – 32138x01 + 30274x02 – 27246x03 + 23170x04 – 18205x05 + 12540x06 – 6393x07 Or: Z(k,0) = (23170xk0 + 30274xk2 + 23170xk4 + 12540xk6) + (32138xk1 + 27246xk3 + 18205xk5 + 6393xk7) = P01 + P02 Z(k,1) = (23170xk0 + 12540xk2 – 23170xk4 – 30274xk6) + (27246xk1 – 6393xk3 – 32138xk5 – 18205xk7) = P11 + P12 Z(k,2) = (23170xk0 – 12540xk2 – 23170xk4 + 30274xk6) + (18205xk1 – 32138xk3 + 6393xk5 + 27246xk7) = P21 + P22 Z(k,3) = (23170xk0 – 30274xk2 + 23170xk4 – 12540xk6) + (6393xk1 – 18205xk3 + 27246xk5 – 32138xk7) = P31 + P32 Z(k,4) = P31 – P32 Z(k,5) = P21 – P22 Z(k,6) = P11 – P12 Z(k,7) = P01 – P02 where k = 0, 2, …, 7

12. P-12/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.1 1D IDCT  The block diagram for the implementation of the 1D IDCT is shown below.

13. P-13/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA I/O Interface Design 6.1 The Implementation of IDCT on FPGA 6.2 AMBA I/O Interface Design 6.3 I/O Interface Design

14. P-14/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA I/O Interface Design  Introduction to the AMBA buses  AMBA AHB bus  AMBA ASB bus  AMBA APB bus

15. P-15/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 Introduction (1/5)  What is AMBA? The Advanced Microcontroller Bus Architecture specification. An on-chip communication standard for designing high- performance embedded microcontroller.  Three distinct buses. AHB (the Advanced High-performance Bus ). High-performance system backbone bus. ASB (the Advanced System Bus ). An alternative system bus. APB (the Advanced Peripheral Bus ). Minimal power consumption. Reduced interface complexity.

16. P-16/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 Introduction (2/5)  Objectives of the AMBA specification. To facilitate the right-first-time development of embedded microcontroller products. To be technology-independent. To ensure that highly reusable peripheral and system. macrocells can be migrated across a diverse range of IC processes. To encourage modular system design. To minimize the silicon infrastructure required for both operation and manufacturing test.

17. P-17/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 Introduction (3/5)  Typical AMBA system. High-bandwidth External Memory Interface High-bandwidth On-chip RAM High-performance ARM-processor DMA bus master BRIDGEBRIDGE UARTTimer KeypadPIO APB AHB or ASB AHB to APB Bridge Or ASB to APB Bridge

18. P-18/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 Introduction (4/5) AMBA AHBAMBA ASBAMBA APB FeatureHigh performance Low power Pipelined operation Latched address and control Multiple bus masters Simple interface Burst transfers Suitable for many peripherals Split transactions Dual-clock edge operation Single-clock edge operation (rising edge) Single-cycle bus master handover Single-clock edge operation (rising edge) Wider data bus configuration ComponentsAHB masterASB master APB bridge (slave on AHB or ASB) AHB slaveASB slaveAPB slave AHB arbiterASB arbiter AHB decoderASB decoder  Feature

19. P-19/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 Introduction (5/5)  When to use AMBA AHB/ASB or APB. A full AHB or ASB. Bus masters. On-chip memory blocks. External memory interface. High-bandwidth peripherals with FIFO interfaces. DMA slave peripherals. A simple APB interface. Simple register-mapped slave devices. Very low power interfaces where clocks cannot be globally routed. Grouping narrow-bus peripherals to avoid loading the system bus.

20. P-20/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA I/O Interface Design  Introduction to the AMBA buses  AMBA AHB bus  AMBA ASB bus  AMBA APB bus

21. P-21/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 A Typical AHB and APB System High-bandwidth Memory Interface High-bandwidth on-chip RAM High-performance ARM-processor DMA bus master BRIDGEBRIDGE UARTTimer KeypadPIO APB AHB AHB to APB Bridge AMBA Advanced High-performance Bus (AHB) *High performance *Pipelined operation *Burst transfers *Multiple bus masters *Split transactions AMBA Advanced Peripheral Bus (APB) *Low power *Latched address and control *Simple interface *Suitable for many peripherals

22. P-22/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA AHB Bus Interconnect  Multiplexor interconnection. HADDR HWDATA HRDATA HADDR HWDATA HRDATA Address and control mux Write data mux Read data mux

23. P-23/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA AHB Transfer Type  Transfer type encoding. HTRANS[1:0] 00 – IDLE No data transfer is required. 01 – BUSY Bus masters insert IDLE cycles in the middle of bursts of transfers. 10 – NONSEQ The first transfer of a burst or a single transfer is initiated. 11 – SEQ The remaining transfers are in a burst. The address is related to the previous transfer.

24. P-24/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 Slave Transfer Responses  Response encoding. HRESP[1:0] 00 – OKAY. 01 – ERROR. 10 – RETRY. The signal shows the transfer has not yet completed, so the bus master should retry the transfer. 11 – SPLIT The slave will request access to the bus on behalf of the master when the transfer can complete.  If the response is the one among ERROR, RETRY and SPLIT, a two-cycle response is required.

25. P-25/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA AHB Bus Arbitration  Bus master grant signals. The HGRANTx signal is only used by the master to determine when it owns the bus. Decoder Master #1 Master #2 Master #3 HGRANT_M1 HGRANT_M2 HGRANT_M3 HADDR_M1[31:0] HADDR_M2[31:0] HADDR_M3[31:0] HADDR to all slaves HMASTER[3:0] Address and Control multiplex Arbiter

26. P-26/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA AHB Bus Slave  AHB bus slave interface. AHB slave Split-capable slave HSELx HADDR[31:0] HWRITE HTRANS[1:0] HSIZE[2:0] HBURST[2:0] HWDATA[31:0] HRESETn HCLK HMASTER[3:0] HMASTLOCK Select Address and control Data Reset Clock HRDATA[31:0] HREADY HRESP[1:0] HSPLITx[15:0] Data Transfer response

27. P-27/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA AHB Bus Master  AHB bus master interface. AHB master HGRANTx HREADY HRESP[1:0] HRESETn HCLK HRDATA[31:0] Arbiter grant Transfer response Reset Clock Data HBUSREQx HLOCKx HTRANS[1:0] HADDR[31:0] HWRITE HSIZE[2:0] HBURST[2:0] HPROT[3:0] HWDATA[31:0] Arbiter Transfer type Address and control Data

28. P-28/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA AHB Arbiter  AHB arbiter interface. AHB arbiter HBUSREQx1 HLOCKx1 HBUSREQx2 HLOCKx2 HBUSREQx3 HLOCKx3 HADDR[31:0] HSPLITx[15:0] HTRANS[1:0] HBURST[2:0] HRESP[1:0] HRESETn HCLK Arbiter requests and locks Address and control Reset Clock HGRANTx1 HGRANTx2 HGRANTx3 HMASTER[3:0] HMASTLOCK Arbiter grants HREADY

29. P-29/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA I/O Interface Design  Introduction to the AMBA buses  AMBA AHB bus  AMBA ASB bus  AMBA APB bus

30. P-30/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 A Typical AMBA ASB-based Microcontroller  A typical AMBA system. High-bandwidth Memory Interface High-bandwidth on-chip RAM High-performance ARM-processor DMA bus master BRIDGEBRIDGE UARTTimer KeypadPIO APB ASB ASB to APB Bridge AMBA Advanced System Bus (ASB) *High performance *Pipelined operation *Burst transfers *Multiple bus masters AMBA Advanced Peripheral Bus (APB) *Low power *Latched address and control *Simple interface *Suitable for many peripherals

31. P-31/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA ASB Description  Basic flow of the bus operation. The arbiter determines which master is granted access to the bus. When granted, a master initiates transfers on the bus. The decoder uses the high order address lines to select a bus slave. The slave provides a transfer response back lines to the bus master and data is transferred between the master and slave.

32. P-32/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 ASB Transfers  Three types of transfer. NONSEQUENTIAL Used for signal transfers or the first transfer of a burst. SEQUENTIAL Used for transfers in a burst. The address of a SEQUENTIAL transfer is always related to the previous transfer. ADDRESS-ONLY Used when no data movement is required.

33. P-33/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA ASB Bus Slave  ASB bus slave interface. ASB slave DSEL Select BA[31:0] BWRITE BSIZE[1:0] BnRES BCLK Address and control Reset Clock BWAIT BERROR BLAST BD[31:0] Transfer response Data

34. P-34/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBS ASB Bus Master  ASB bus master interface. ASB master AGNT BWAIT BERROR BLAST BnRES BCLK Arbiter grant Transfer response Reset Clock AREQ BLOK BTRAN[1:0] BA[31:0] BWRITE BSIZE[1:0] BPROT[1:0] BD[31:0] Arbiter Transfer type Address and control Data

35. P-35/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA ASB Bus Decoder  ASB decoder interface. ASB decoder BTRAN[1:0] BA[31:0] BWRITE BSIZE[1:0] BPROT[1:0] BnRES BCLK Transfer type Address and control Reset Clock DSEL1 ….. DSELn BWAIT BERROR BLAST Selects Transfer response

36. P-36/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA ASB Bus Arbiter  ASB arbiter interface. ASB arbiter AREQx1 AREQx2 AREQx3 BWAIT BLOK BnRES BCLK Arbiter requests Wait Lock Reset Clock AGNTx1 AGNTx2 AGNTx3 Arbiter grants

37. P-37/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA I/O Interface Design  Introduction to the AMBA buses  AMBA AHB bus  AMBA ASB bus  AMBA APB bus

38. P-38/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 A Typical AMBA-based Microcontroller  AMBA Advanced Peripheral Bus (APB). High-bandwidth Memory Interface High-bandwidth on-chip RAM High-performance ARM-processor DMA bus master BRIDGEBRIDGE UARTTimer KeypadPIO APB AHB or ASB APB Bridge AMBA Advanced Peripheral Bus (APB) *Low power *Latched address and control *Simple interface *Suitable for many peripherals

39. P-39/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 Avtivity of the Peripheral Bus  State diagram. IDLE The default state for the peripheral bus. SETUP The bus moves into this state when a transfer is required. The bus remains in the SETUP state for one clock and will always move to the ENABLE state. PSELx is asserted. ENABLE PENABLE is asserted. The address, write and select signals all remain stable during SETUP  ENABLE. Glitch is acceptable during ENABLE  SETUP. No transfer Transfer No transfer

40. P-40/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA APB Interface Design  APB bridge interface. APB slave PRDATA PSEL1 PSEL2 PSELn...... PENABLE PADDR PWRITE Selects Strobe Address and control Write data System bus slave interface PRDATARead data PRESETn PCLK Reset Clock

41. P-41/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.2 AMBA APB Slave  APB slave interface. APB slave PRDATA Read data PADDR PWDATA PSELx PENABLE PWRITE PRESETn PCLK Select Strobe Address and control Reset Clock Write data

42. P-42/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 I/O Interface Design 6.1 The Implementation of IDCT on FPGA 6.2 AMBA I/O Interface Design 6.3 I/O Interface Design

43. P-43/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 I/O Interface  Provides a method for transferring information between CPU (or internal storage) and external I/O devices.  I/O devices connected to a computer need special communication links for interfacing them with the CPU.

44. P-44/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Purposes of the Communication Link  Conversion of signal values. The manner of operation for an I/O device may be different from the operation of the CPU.  Providing a synchronization mechanism. The data transfer rate of I/O devices is usually slower than the transfer rate of the CPU.  Word format transformation. Data codes and formats in I/O differ from the word format in the CPU.  The control of I/O devices. To ensure the operation of an I/O device is not disturbed by another I/O devices.

45. P-45/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 I/O Bus and Interface Modules  The I/O bus consists of data lines, address lines, and control lines.

46. P-46/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 I/O versus Memory Bus  There are three ways that computer buses can be used to communicate with memory and I/O: Use two separate buses, one for memory and the other for I/O. Use one common bus for both memory and I/O but have separate control lines for each. Use one common bus for memory and I/O with common control lines.

47. P-47/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Isolated versus Memory-Mapped I/O  Isolated I/O. Isolate all I/O interface addresses from the addresses assigned to memory. Distinct input and output instructions for I/O transfer.  Memory-mapped I/O. Use the same address space for both memory and I/O. No specific input or output instructions. The CPU manipulates I/O data with the same instructions that are used to manipulate memory words.

48. P-48/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Example of I/O Interface CS RS1 RS0Register selected 0 X X None: data bus in high-impedance 1 0 0 Port A register 1 0 1 Port B register 1 1 0 Control register 1 1 1 Status register

49. P-49/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Asynchronous Data Transfer  Asynchronous data transfer between two independent units requires control signals to transmit data.  Two different types of control mechanism for data transferring between two independent units. Strobe control. Handshaking.

50. P-50/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Strobe Control (1/3)  The strobe control method employs a single control line to time each transfer.  The strobe may be activated by either the source or the destination.

51. P-51/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計  Source-initiated strobe for data transfer. 6.3 Strobe Control (2/3) Source unit Destination unit Data bus Strobe (a) Block diagram Data Strobe Valid data (b) Timing diagram

52. P-52/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計  Destination-initiated strobe for data transfer. 6.3 Strobe Control (3/3) Source unit Destination unit Data bus Strobe (a) Block diagram Data Strobe Valid data (b) Timing diagram

53. P-53/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Problem of Strobe Method  The disadvantage of the strobe method is that the source (destination) unit that initiates the transfer has no way of knowing whether the destination (source) unit has actually received the data item that was placed in the bus.

54. P-54/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Handshaking  The basic principle of the two-wire handshaking method of data transfer is as follows. One control line from the source unit is used to inform the destination whether there are valid data in the bus. The other control line from the destination unit is used to inform the source whether it can accept data.

55. P-55/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Data Transfer by Handshaking (1/2)  Data transfer procedure initiated by the source. Source unit Destination unit Data bus Data accepted (a) Block diagram Data valid Data bus Valid data (b) Timing diagram Data valid Data accepted Place data on bus. Enable data valid. Disable data valid. Invalidate data on bus. Accept data from bus. Enable data accepted. Disable data accepted. Ready to accept data (initial state). (c) Sequence of events Source unitDestination unit

56. P-56/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Data Transfer by Handshaking (2/2)  Data transfer procedure initiated by the destination. Source unit Destination unit Data bus Ready for data (a) Block diagram Data valid Ready for bus Valid data (b) Timing diagram Data valid Data bus Place data on bus. Enable data valid. Disable data valid. Invalidate data on bus (initial state). Ready to accept data. Enable ready for data. Accept data from bus. Disable ready for data. (c) Sequence of events Source unit Destination unit

57. P-57/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Asynchronous Serial Transfer  A serial asynchronous data transmission technique employs special bits that are inserted at both ends of the character code.  With this technique, each character consists of three parts: A start bit. The character bits. Stop bits. 11 110000 Start bit Character bits Stop bits

58. P-58/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Asynchronous Communication Interface CSRS 0 X Operation Register selected X None ： data bus in high-impedance 1 0 WR Transmitter register 1 WR Control register 1 0 RD Receiver register 1 RD Status register

59. P-59/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Modes of Transfer  Data transfer to and from I/O devices may be handled in one of three possible modes. Programmed I/O. Interrupt-initiated I/O. Direct memory access (DMA).

60. P-60/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Programmed I/O  Programmed I/O operations are the result of I/O instructions written in the computer program.  Each data item transfer is initiated by an instruction in the program.  Transferring data under program control requires constant monitoring of the I/O by the CPU.  The I/O device does not have direct access to memory.

61. P-61/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Example of Programmed I/O  The steps of data transfer. I/O device places data to the I/O bus and enables the data valid line. The interface accepts the data into its register and enables the data accepted line. The interface sets a bit of flag “F”. The CPU reads the data from the interface according to flag “F”. CPU Interface Data bus Address bus I/O read I/O write Data register Status register F F = Flag bit I/O device I/O bus Data valid Data accepted

62. P-62/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Flowchart for CPU Reads Data From I/O Read data register Check flag bit Flag Read status register Transfer data to memory Operation Complete? Continue with program = 0 = 1 yes no

63. P-63/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Interrupt-Initiated I/O  Instead of constantly monitoring the flag, the CPU is informed to receive data when an interrupt signal happens from the interface.  The CPU responds to the interrupt signal by storing the return address from the program counter into a memory stack and then control branches to a service routine that processes the required I/O transfer.

64. P-64/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Priority Interrupt  The system establishes a priority over the various sources to determine which condition is to be serviced first when two or more requests arrive simultaneously.  Two methods of priority interrupt. Software priority-interrupt. A polling procedure. Hardware priority-interrupt. Daisy-chaining priority. Parallel priority-interrupt.

65. P-65/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Daisy-Chain Priority Interrupt Processor data bus

66. P-66/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Parallel Priority-Interrupt

67. P-67/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 DMA  Removing the CPU from the path and letting the I/O devices manage the memory directly.  During DMA transfer, the CPU is idle and has no control of the memory buses.  Two signals are used to facilitate the DMA transfer. Bus request: a signal from DMA controller. Bus grant: the CPU informs the DMA that the buses are in high-impedance state. BR BG CPU DBUS ABUS RD WR Bus request Bus grant Address bus Data bus Read Write High-impedance (disable) when BG is enable

68. P-68/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 DMA Controller  Block diagram of DMA controller. Data bus buffer Control logic DS RS RD WR BR BG Interrupt DMA select Register select Data bus Internal bus Address bus Read Write Bus request Bus grant Interrupt DMA request DMA Acknowledge Address bus buffer Address register Word count register Control register to I/O device

69. P-69/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 Initialization of DMA  The CPU initializes the DMA by sending the following information through the data bus. Starting address of the memory block. Word count. Mode of transfer. A start signal to do DMA transfer.

70. P-70/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 6.3 DMA Transfer CPU WRAddressDataRD Random-access memory (RAM) WRAddressDataRD Direct memory access (DMA) controller WRAddressDataRD DS RS BR BG Interrupt Address select Read control Write control Data bus Address bus Interrupt BG BR I/O Peripheral device DMA acknowledge DMA request

71. P-71/93 教育部顧問室 PAL 聯盟 / 系統雛型與軟硬體整合設計第六章： FPGA 模組與硬體介面設計 References  http://www.xilinx.com/bvdocs/appnotes/xapp611.pdf  http://www.arm.com/products/solutions/AMBA_Spec.html  Mano, M. Morris, “Computer system architecture,” Prentice Hall,1993.