1. CS152 / Kubiatowicz Lec5.1 9/14/01©UCB Fall 2001 CS152 Computer Architecture and Engineering Lecture 5 VHDL, Multiply, Shift September 14, 2001 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/

2. CS152 / Kubiatowicz Lec5.2 9/14/01©UCB Fall 2001 Today’s Outline °Review of Last lecture °on-line lab notebook °Intro to VHDL °Administrative Issues °Designing a Multiplier °Booth’s algorithm °Shifters

3. CS152 / Kubiatowicz Lec5.3 9/14/01©UCB Fall 2001 Review: ALU Design °Bit-slice plus extra on the two ends °Overflow means number too large for the representation °Carry-look ahead and other adder tricks A M S 32 4 Ovflw ALU0 a0b0 cinco s0 ALU31 a31b31 cinco s31 B32 C/L to produce select, comp, c-in signed-arith and cin xor co

4. CS152 / Kubiatowicz Lec5.4 9/14/01©UCB Fall 2001 Review: Elements of the Design Process °Divide and Conquer (e.g., ALU) Formulate a solution in terms of simpler components. Design each of the components (subproblems) °Generate and Test (e.g., ALU) Given a collection of building blocks, look for ways of putting them together that meets requirement °Successive Refinement (e.g., multiplier, divider) Solve "most" of the problem (i.e., ignore some constraints or special cases), examine and correct shortcomings. °Formulate High-Level Alternatives (e.g., shifter) Articulate many strategies to "keep in mind" while pursuing any one approach. °Work on the Things you Know How to Do The unknown will become “obvious” as you make progress.

5. CS152 / Kubiatowicz Lec5.5 9/14/01©UCB Fall 2001 Review: Summary of the Design Process Hierarchical Design to manage complexity Top Down vs. Bottom Up vs. Successive Refinement Importance of Design Representations: Block Diagrams Decomposition into Bit Slices Truth Tables, K-Maps Circuit Diagrams Other Descriptions: state diagrams, timing diagrams, reg xfer,... Optimization Criteria: Gate Count [Package Count] Logic Levels Fan-in/Fan-out Power top down bottom up Area Delay CostDesign timePin Out

6. CS152 / Kubiatowicz Lec5.6 9/14/01©UCB Fall 2001 Why should you keep an design notebook? °Keep track of the design decisions and the reasons behind them Otherwise, it will be hard to debug and/or refine the design Write it down so that can remember in long project: 2 weeks ->2 yrs Others can review notebook to see what happened °Record insights you have on certain aspect of the design as they come up °Record of the different design & debug experiments Memory can fail when very tired °Industry practice: learn from others mistakes

7. CS152 / Kubiatowicz Lec5.7 9/14/01©UCB Fall 2001 Why do we keep it on-line? °You need to force yourself to take notes Open a window and leave an editor running while you work 1) Acts as reminder to take notes 2) Makes it easy to take notes 1) + 2) => will actually do it °Take advantage of the window system’s “cut and paste” features °It is much easier to read your typing than your writing °Also, paper log books have problems Limited capacity => end up with many books May not have right book with you at time vs. networked screens Can use computer to search files/index files to find what looking for

8. CS152 / Kubiatowicz Lec5.8 9/14/01©UCB Fall 2001 How should you do it? °Keep it simple DON’T make it so elaborate that you won’t use (fonts, layout,...) °Separate the entries by dates type “ date ” command in another window and cut&paste °Start day with problems going to work on today °Record output of simulation into log with cut&paste; add date May help sort out which version of simulation did what °Record key email with cut&paste °Record of what works & doesn’t helps team decide what went wrong after you left °Index: write a one-line summary of what you did at end of each day

9. CS152 / Kubiatowicz Lec5.9 9/14/01©UCB Fall 2001 On-line Notebook Example Refer to the handout: “Example of On-Line Log Book” on cs152 home page (handouts section)

10. CS152 / Kubiatowicz Lec5.10 9/14/01©UCB Fall 2001 1st page of On-line notebook (Index + Wed. 9/6/95) * Index ============================================================== Wed Sep 6 00:47:28 PDT 1995 - Created the 32-bit comparator component Thu Sep 7 14:02:21 PDT 1995 - Tested the comparator Mon Sep 11 12:01:45 PDT 1995 - Investigated bug found by Bart in comp32 and fixed it + ==================================================================== Wed Sep 6 00:47:28 PDT 1995 Goal: Layout the schematic for a 32-bit comparator I've layed out the schemtatics and made a symbol for the comparator. I named it comp32. The files are ~/wv/proj1/sch/comp32.sch ~/wv/proj1/sch/comp32.sym Wed Sep 6 02:29:22 PDT 1995 - ==================================================================== Add 1 line index at front of log file at end of each session: date+summary Start with date, time of day + goal Make comments during day, summary of work End with date, time of day (and add 1 line summary at front of file)

11. CS152 / Kubiatowicz Lec5.11 9/14/01©UCB Fall 2001 2nd page of On-line notebook (Thursday 9/7/95) + ==================================================================== Thu Sep 7 14:02:21 PDT 1995 Goal: Test the comparator component I've written a command file to test comp32. I've placed it in ~/wv/proj1/diagnostics/comp32.cmd. I ran the command file in viewsim and it looks like the comparator is working fine. I saved the output into a log file called ~/wv/proj1/diagnostics/comp32.log Notified the rest of the group that the comparator is done. Thu Sep 7 16:15:32 PDT 1995 - ====================================================================

12. CS152 / Kubiatowicz Lec5.12 9/14/01©UCB Fall 2001 3rd page of On-line notebook (Monday 9/11/95) + ==================================================================== Mon Sep 11 12:01:45 PDT 1995 Goal: Investigate bug discovered in comp32 and hopefully fix it Bart found a bug in my comparator component. He left the following e-mail. ------------------- From bart@simpsons.residence Sun Sep 10 01:47:02 1995 Received: by wayne.manor (NX5.67e/NX3.0S) id AA00334; Sun, 10 Sep 95 01:47:01 -0800 Date: Wed, 10 Sep 95 01:47:01 -0800 From: Bart Simpson To: bruce@wanye.manor, old_man@gokuraku, hojo@sanctuary Subject: [cs152] bug in comp32 Status: R Hey Bruce, I think there's a bug in your comparator. The comparator seems to think that ffffffff and fffffff7 are equal. Can you take a look at this? Bart ----------------

13. CS152 / Kubiatowicz Lec5.13 9/14/01©UCB Fall 2001 4th page of On-line notebook (9/11/95 contd) I verified the bug. here's a viewsim of the bug as it appeared.. (equal should be 0 instead of 1) ------------------ SIM>stepsize 10ns SIM>v a_in A[31:0] SIM>v b_in B[31:0] SIM>w a_in b_in equal SIM>a a_in ffffffff\h SIM>a b_in fffffff7\h SIM>sim time = 10.0ns A_IN=FFFFFFFF\H B_IN=FFFFFFF7\H EQUAL=1 Simulation stopped at 10.0ns. ------------------- Ah. I've discovered the bug. I mislabeled the 4th net in the comp32 schematic. I corrected the mistake and re-checked all the other labels, just in case. I re-ran the old diagnostic test file and tested it against the bug Bart found. It seems to be working fine. hopefully there aren’t any more bugs:)

14. CS152 / Kubiatowicz Lec5.14 9/14/01©UCB Fall 2001 5th page of On-line notebook (9/11/95 contd) On second inspectation of the whole layout, I think I can remove one level of gates in the design and make it go faster. But who cares! the comparator is not in the critical path right now. the delay through the ALU is dominating the critical path. so unless the ALU gets a lot faster, we can live with a less than optimal comparator. I e-mailed the group that the bug has been fixed Mon Sep 11 14:03:41 PDT 1995 - ==================================================================== Perhaps later critical path changes; what was idea to make compartor faster? Check log book!

15. CS152 / Kubiatowicz Lec5.15 9/14/01©UCB Fall 2001 Added benefit: cool post-design statistics Sample graph from the Alewife project: For the Communications and Memory Management Unit (CMMU) These statistics came from on-line record of bugs

16. CS152 / Kubiatowicz Lec5.16 9/14/01©UCB Fall 2001 Hardware Representation Languages: Block Diagrams: FUs, Registers, & Dataflows Register Transfer Diagrams: Choice of busses to connect FUs, Regs Flowcharts State Diagrams Fifth Representation "Language": Hardware Description Languages E.G., ISP' VHDL Verilog Descriptions in these languages can be used as input to simulation systems synthesis systems Representation Languages Two different ways to describe sequencing & microoperations hw modules described like programs with i/o ports, internal state, & parallel execution of assignment statements "software breadboard" generate hw from high level description "To Design is to Represent"

17. CS152 / Kubiatowicz Lec5.17 9/14/01©UCB Fall 2001 Simulation Before Construction "Physical Breadboarding" discrete components/lower scale integration preceeds actual construction of prototype verify initial design concept No longer possible as designs reach higher levels of integration! Simulation Before Construction high level constructs implies faster to construct play "what if" more easily limited performance accuracy, however

18. CS152 / Kubiatowicz Lec5.18 9/14/01©UCB Fall 2001 Levels of Description Architectural Simulation Functional/Behavioral Register Transfer Logic Circuit models programmer's view at a high level; written in your favorite programming language more detailed model, like the block diagram view commitment to datapath FUs, registers, busses; register xfer operations are clock phase accurate model is in terms of logic gates; higher level MSI functions described in terms of these electrical behavior; accurate waveforms Schematic capture + logic simulation package like Powerview Special languages + simulation systems for describing the inherent parallel activity in hardware Less Abstract More Accurate Slower Simulation

19. CS152 / Kubiatowicz Lec5.19 9/14/01©UCB Fall 2001 VHDL (VHSIC Hardware Description Language) °Goals: Support design, documentation, and simulation of hardware Digital system level to gate level “Technology Insertion” °Concepts: Design entity Time-based execution model. Design Entity == Hardware Component Interface == External Characteristics Architecture (Body ) == Internal Behavior or Structure

20. CS152 / Kubiatowicz Lec5.20 9/14/01©UCB Fall 2001 Interface °Externally Visible Characterisitcs Ports: channels of communication -(inputs, outputs, clocks, control) Generic Parameters: define class of components -(timing characterisitcs, size, fan-out) --- determined where instantiated or by default °Internally Visible Characteristics Declarations: Assertions: constraints on all alternative bodies (i.e., implementations) Interface Architecture view to other modules details of implementation

21. CS152 / Kubiatowicz Lec5.21 9/14/01©UCB Fall 2001 VHDL Example: nand gate °Entity describes interface °Architecture give behavior, i.e., function °y is a signal, not a variable it changes when ever the inputs change drive a signal NAND process is in an infinite loop °VLBit is 0, 1, X or Z ENTITY nand is PORT (a,b: IN VLBIT; y: OUT VLBIT) END nand ARCHITECTURE behavioral OF nand is BEGIN y < = a NAND b; END behavioral;

22. CS152 / Kubiatowicz Lec5.22 9/14/01©UCB Fall 2001 Modeling Delays °Model temporal, as well as functional behavior, with delays in signal statements; Time is one difference from programming languages °y changes 1 ns after a or b changes °This fixed delay is inflexible hard to reflect changes in technology ENTITY nand is PORT (a,b: IN VLBIT; y: OUT VLBIT) END nand ARCHITECTURE behavioral OF nand is BEGIN y < = a NAND b after 1 ns; END behavioral;

23. CS152 / Kubiatowicz Lec5.23 9/14/01©UCB Fall 2001 Generic Parameters °Generic parameters provide default values may be overridden on each instance attach value to symbol as attribute °Separate functional and temporal models °How would you describe fix-delay + slope * load model? ENTITY nand is GENERIC (delay: TIME := 1ns); PORT (a,b: IN VLBIT; y: OUT VLBIT) END nand ARCHITECTURE behavioral OF nand is BEGIN y <= a NAND b AFTER delay; END behavioral;

24. CS152 / Kubiatowicz Lec5.24 9/14/01©UCB Fall 2001 Bit-vector data type VLBIT_1D ( 31 downto 0) is equivalent to powerview 32-bit bus Can convert it to a 32 bit integer ENTITY nand32 is PORT (a,b: IN VLBIT_1D ( 31 downto 0); y: OUT VLBIT_1D ( 31 downto 0) END nand32 ARCHITECTURE behavioral OF nand32 is BEGIN y < = a NAND b; END behavioral;

25. CS152 / Kubiatowicz Lec5.25 9/14/01©UCB Fall 2001 Arithmetic Operations °addum (see VHDL ref. appendix C) adds two n-bit vectors to produce an n+1 bit vector except when n = 32! ENTITY add32 is PORT (a,b: IN VLBIT_1D ( 31 downto 0); y: OUT VLBIT_1D ( 31 downto 0) END add32 ARCHITECTURE behavioral OF add32 is BEGIN y < = addum(a, b) ; END behavioral;

26. CS152 / Kubiatowicz Lec5.26 9/14/01©UCB Fall 2001 Control Constructs °Process fires whenever is “sensitivity list” changes °Evaluates the body sequentially °VHDL provide case statements as well entity MUX32X2 is generic (output_delay : TIME := 4 ns); port(A,B:in vlbit_1d(31 downto 0); DOUT:out vlbit_1d(31 downto 0); SEL:in vlbit); end MUX32X2; architecture behavior of MUX32X2 is begin mux32x2_process: process(A, B, SEL) begin if (vlb2int(SEL) = 0) then DOUT <= A after output_delay; else DOUT <= B after output_delay; end if; end process; end behavior;

27. CS152 / Kubiatowicz Lec5.27 9/14/01©UCB Fall 2001 Administrative Matters °Remember that first homework due next Wednesday First homework quiz at BEGINNING of class. No late homework (No exceptions) °First Lab due next Wednesday at midnight via submit program No late labs! Mount filesystem as \\fileservice\cs152 °On-line lab notebook is such a good idea, its required! (starting with Lab 3) °Reading Chapter 4 now

28. CS152 / Kubiatowicz Lec5.28 9/14/01©UCB Fall 2001 MIPS arithmetic instructions °InstructionExampleMeaningComments °add add $1,$2,$3$1 = $2 + $33 operands; exception possible °subtractsub $1,$2,$3$1 = $2 – $33 operands; exception possible °add immediateaddi $1,$2,100$1 = $2 + 100+ constant; exception possible °add unsignedaddu $1,$2,$3$1 = $2 + $33 operands; no exceptions °subtract unsignedsubu $1,$2,$3$1 = $2 – $33 operands; no exceptions °add imm. unsign.addiu $1,$2,100$1 = $2 + 100+ constant; no exceptions °multiply mult $2,$3Hi, Lo = $2 x $364-bit signed product °multiply unsignedmultu$2,$3Hi, Lo = $2 x $3 64-bit unsigned product °divide div $2,$3Lo = $2 ÷ $3,Lo = quotient, Hi = remainder ° Hi = $2 mod $3 °divide unsigned divu $2,$3Lo = $2 ÷ $3,Unsigned quotient & remainder ° Hi = $2 mod $3 °Move from Himfhi $1$1 = HiUsed to get copy of Hi °Move from Lomflo $1$1 = LoUsed to get copy of Lo

29. CS152 / Kubiatowicz Lec5.29 9/14/01©UCB Fall 2001 MULTIPLY (unsigned) °Paper and pencil example (unsigned): Multiplicand 1000 Multiplier 1001 1000 0000 0000 1000 Product 01001000 °m bits x n bits = m+n bit product °Binary makes it easy: 0 => place 0 ( 0 x multiplicand) 1 => place a copy ( 1 x multiplicand) °4 versions of multiply hardware & algorithm: successive refinement

30. CS152 / Kubiatowicz Lec5.30 9/14/01©UCB Fall 2001 Unsigned Combinational Multiplier °Stage i accumulates A * 2 i if B i == 1 °Q: How much hardware for 32 bit multiplier? Critical path? B0B0 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000

31. CS152 / Kubiatowicz Lec5.31 9/14/01©UCB Fall 2001 How does it work? °at each stage shift A left ( x 2) °use next bit of B to determine whether to add in shifted multiplicand °accumulate 2n bit partial product at each stage B0B0 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000 000

32. CS152 / Kubiatowicz Lec5.32 9/14/01©UCB Fall 2001 Unisigned shift-add multiplier (version 1) °64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Product Multiplier Multiplicand 64-bit ALU Shift Left Shift Right Write Control 32 bits 64 bits Multiplier = datapath + control

33. CS152 / Kubiatowicz Lec5.33 9/14/01©UCB Fall 2001 Multiply Algorithm Version 1 °ProductMultiplierMultiplicand 0000 0000 00110000 0010 °0000 001000010000 0100 °0000 011000000000 1000 °0000 0110 3. Shift the Multiplier register right 1 bit. Done Yes: 32 repetitions 2. Shift the Multiplicand register left 1 bit. No: < 32 repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to product & place the result in Product register 32nd repetition? Start

34. CS152 / Kubiatowicz Lec5.34 9/14/01©UCB Fall 2001 Observations on Multiply Version 1 °1 clock per cycle =>  100 clocks per multiply Ratio of multiply to add 5:1 to 100:1 °1/2 bits in multiplicand always 0 => 64-bit adder is wasted °0’s inserted in left of multiplicand as shifted => least significant bits of product never changed once formed °Instead of shifting multiplicand to left, shift product to right?

35. CS152 / Kubiatowicz Lec5.35 9/14/01©UCB Fall 2001 MULTIPLY HARDWARE Version 2 °32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg Product Multiplier Multiplicand 32-bit ALU Shift Right Write Control 32 bits 64 bits Shift Right

36. CS152 / Kubiatowicz Lec5.36 9/14/01©UCB Fall 2001 How to think of this? B0B0 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000 Remember original combinational multiplier:

37. CS152 / Kubiatowicz Lec5.37 9/14/01©UCB Fall 2001 Simply warp to let product move right... °Multiplicand stay’s still and product moves right B0B0 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3

38. CS152 / Kubiatowicz Lec5.38 9/14/01©UCB Fall 2001 Multiply Algorithm Version 2 3. Shift the Multiplier register right 1 bit. Done Yes: 32 repetitions 2. Shift the Product register right 1 bit. No: < 32 repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 32nd repetition? Start 0000 0000 0011 0010 1: 0010 0000 0011 0010 2: 0001 0000 0011 0010 3: 0001 0000 0001 0010 1: 0011 0000 0001 0010 2: 0001 1000 0001 0010 3: 0001 1000 0000 0010 1: 0001 1000 0000 0010 2: 0000 1100 0000 0010 3: 0000 1100 0000 0010 1: 0000 1100 0000 0010 2: 0000 0110 0000 0010 3: 0000 0110 0000 0010 0000 0110 0000 0010 Product Multiplier Multiplicand

39. CS152 / Kubiatowicz Lec5.39 9/14/01©UCB Fall 2001 Still more wasted space! 3. Shift the Multiplier register right 1 bit. Done Yes: 32 repetitions 2. Shift the Product register right 1 bit. No: < 32 repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 32nd repetition? Start 0000 0000 0011 0010 1: 0010 0000 0011 0010 2: 0001 0000 0011 0010 3: 0001 0000 0001 0010 1: 0011 0000 0001 0010 2: 0001 1000 0001 0010 3: 0001 1000 0000 0010 1: 0001 1000 0000 0010 2: 0000 1100 0000 0010 3: 0000 1100 0000 0010 1: 0000 1100 0000 0010 2: 0000 0110 0000 0010 3: 0000 0110 0000 0010 0000 0110 0000 0010 Product Multiplier Multiplicand

40. CS152 / Kubiatowicz Lec5.40 9/14/01©UCB Fall 2001 Observations on Multiply Version 2 °Product register wastes space that exactly matches size of multiplier => combine Multiplier register and Product register

41. CS152 / Kubiatowicz Lec5.41 9/14/01©UCB Fall 2001 MULTIPLY HARDWARE Version 3 °32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg) Product (Multiplier) Multiplicand 32-bit ALU Write Control 32 bits 64 bits Shift Right

42. CS152 / Kubiatowicz Lec5.42 9/14/01©UCB Fall 2001 Multiply Algorithm Version 3 MultiplicandProduct 00100000 0011 Done Yes: 32 repetitions 2. Shift the Product register right 1 bit. No: < 32 repetitions 1. Test Product0 Product0 = 0 Product0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 32nd repetition? Start

43. CS152 / Kubiatowicz Lec5.43 9/14/01©UCB Fall 2001 Observations on Multiply Version 3 °2 steps per bit because Multiplier & Product combined °MIPS registers Hi and Lo are left and right half of Product °Gives us MIPS instruction MultU °How can you make it faster? °What about signed multiplication? easiest solution is to make both positive & remember whether to complement product when done (leave out the sign bit, run for 31 steps) apply definition of 2’s complement -need to sign-extend partial products and subtract at the end Booth’s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles -can handle multiple bits at a time

44. CS152 / Kubiatowicz Lec5.44 9/14/01©UCB Fall 2001 Motivation for Booth’s Algorithm °Example 2 x 6 = 0010 x 0110: 0010 x 0110 + 0000shift (0 in multiplier) + 0010 add (1 in multiplier) + 0010 add (1 in multiplier) + 0000 shift (0 in multiplier) 00001100 °ALU with add or subtract gets same result in more than one way: 6= – 2 + 8 0110 = – 00010 + 01000 = 11110 + 01000 °For example ° 0010 x 0110 0000 shift (0 in multiplier) – 0010 sub (first 1 in multpl.). 0000 shift (mid string of 1s). +0010 add (prior step had last 1) 00001100

45. CS152 / Kubiatowicz Lec5.45 9/14/01©UCB Fall 2001 Booth’s Algorithm Current BitBit to the RightExplanationExampleOp 10Begins run of 1s0001111000sub 11Middle of run of 1s0001111000none 01End of run of 1s0001111000add 00Middle of run of 0s0001111000none Originally for Speed (when shift was faster than add) °Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one 0 1 1 1 1 0 beginning of runend of run middle of run –1 + 10000 01111

46. CS152 / Kubiatowicz Lec5.46 9/14/01©UCB Fall 2001 Booths Example (2 x 7) 1a. P = P - m1110 +1110 1110 0111 0shift P (sign ext) 1b. 00101111 0011 111 -> nop, shift 2.00101111 1001 111 -> nop, shift 3.00101111 1100 101 -> add 4a.0010 +0010 0001 1100 1shift 4b.00100000 1110 0done OperationMultiplicandProductnext? 0. initial value00100000 0111 010 -> sub

47. CS152 / Kubiatowicz Lec5.47 9/14/01©UCB Fall 2001 Booths Example (2 x -3) 1a. P = P - m1110 +1110 1110 1101 0shift P (sign ext) 1b. 00101111 0110 101 -> add + 0010 2a.0001 0110 1shift P 2b.00100000 1011 010 -> sub +1110 3a.00101110 1011 0shift 3b.0010 1111 0101 111 -> nop 4a1111 0101 1 shift 4b.00101111 1010 1 done OperationMultiplicandProductnext? 0. initial value00100000 1101 010 -> sub

48. CS152 / Kubiatowicz Lec5.48 9/14/01©UCB Fall 2001 MIPS logical instructions °InstructionExampleMeaningComment °and and $1,$2,$3$1 = $2 & $33 reg. operands; Logical AND °or or $1,$2,$3$1 = $2 | $33 reg. operands; Logical OR °xor xor $1,$2,$3$1 = $2  $33 reg. operands; Logical XOR °nor nor $1,$2,$3$1 = ~($2 |$3)3 reg. operands; Logical NOR °and immediate andi $1,$2,10$1 = $2 & 10Logical AND reg, constant °or immediate ori $1,$2,10$1 = $2 | 10Logical OR reg, constant °xor immediate xori $1, $2,10 $1 = ~$2 &~10Logical XOR reg, constant °shift left logical sll $1,$2,10$1 = $2 << 10Shift left by constant °shift right logical srl $1,$2,10$1 = $2 >> 10Shift right by constant °shift right arithm. sra $1,$2,10$1 = $2 >> 10Shift right (sign extend) °shift left logical sllv $1,$2,$3$1 = $2 << $3 Shift left by variable °shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable °shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

49. CS152 / Kubiatowicz Lec5.49 9/14/01©UCB Fall 2001 Shifters Two kinds: logical-- value shifted in is always "0" arithmetic-- on right shifts, sign extend msblsb"0" msblsb"0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!

50. CS152 / Kubiatowicz Lec5.50 9/14/01©UCB Fall 2001 Combinational Shifter from MUXes °What comes in the MSBs? °How many levels for 32-bit shifter? °What if we use 4-1 Muxes ? 1 0 sel A B D Basic Building Block 8-bit right shifter 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 S 2 S 1 S 0 A0A0 A1A1 A2A2 A3A3 A4A4 A5A5 A6A6 A7A7 R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7

51. CS152 / Kubiatowicz Lec5.51 9/14/01©UCB Fall 2001 General Shift Right Scheme using 16 bit example If added Right-to-left connections could support Rotate (not in MIPS but found in ISAs)

52. CS152 / Kubiatowicz Lec5.52 9/14/01©UCB Fall 2001 Funnel Shifter XY R °Shift A by i bits (sa= shift right amount) °Logical: Y = 0, X=A, sa=i °Arithmetic? Y = _, X=_, sa=_ °Rotate? Y = _, X=_, sa=_ °Left shifts? Y = _, X=_, sa=_ Instead Extract 32 bits of 64. Shift Right 32 Y X R

53. CS152 / Kubiatowicz Lec5.53 9/14/01©UCB Fall 2001 Barrel Shifter Technology-dependent solutions: transistor per switch

54. CS152 / Kubiatowicz Lec5.54 9/14/01©UCB Fall 2001 Summary °Intro to VHDL a language to describe hardware -entity = symbol, architecture ~ schematic, signals = wires behavior can be higher level -x <= boolean_expression(A,B,C,D); Has time as concept Can activate when inputs change, not specifically invoked Inherently parallel °Multiply: successive refinement to see final design 32-bit Adder, 64-bit shift register, 32-bit Multiplicand Register Booth’s algorithm to handle signed multiplies There are algorithms that calculate many bits of multiply per cycle (see exercises 4.36 to 4.39 in COD) °Shifter: success refinement 1/bit at a time shift register to barrel shifter °What’s Missing from MIPS is Divide & Floating Point Arithmetic: Next time the Pentium Bug

55. CS152 / Kubiatowicz Lec5.55 9/14/01©UCB Fall 2001 To Get More Information °Chapter 4 of your text book: David Patterson & John Hennessy, “Computer Organization & Design,” Morgan Kaufmann Publishers, 1994. °David Winkel & Franklin Prosser, “The Art of Digital Design: An Introduction to Top-Down Design,” Prentice-Hall, Inc., 1980. °Kai Hwang, “Computer Arithmetic: Principles, archtiecture, and design”, Wiley 1979