1. 1 Distributed Loss Compensation for Low-latency On-chip Interconnects Class Presentation For Advanced VLSI Design Course Instructor: Dr.Fakhraie Presented By: Fahimeh Alsadat Hoseini Winter 2006 University of Tehran Dept. Electrical and Computer Enginerring Major Reference: ISSCC 2006 / SESSION 21 / ADVANCED CLOCKING, LOGIC AND SIGNALING TECHNIQUES / 21.7

2. 2 Outline  Scaling trends and motivation  Prior work on low-latency repeater-less links by exploiting transmission-line behavior  Negative-impedance converter (NIC)  System architecture  Transmitter design  Receiver design  Measurement results  Summary and conclusions  References

3. 3 Scaling Trends - ITRS Roadmap  On-chip wire delay scaling more slowly than gate delay.  Impact of scaling is worst on global wiring. Jose et al., ISSCC, 2006.

4. 4 Motivation  Wire delays (D) grow quadratically with wire length, - Unacceptably great for long wires. - Wire bandwidths,which are inversely proportional to D, degrade.  Latency is controlled with repeater insertion which allows linear scaling of delay with length. -Break long wires into N shorter segments - Drive each one with an inverter or buffer -Optimal number of repeaters can be determined to minimize delay -Repeaters, often inserted with CAD tools, consume a significant fraction of on-chip power and area in microprocessors.

5. 5 Outline  Scaling trends and motivation  Prior work on low-latency repeater-less links by exploiting transmission-line behavior  Negative-impedance converter (NIC)  System architecture  Transmitter design  Receiver design  Measurement results  Summary and conclusions  References

6. 6 Nearly ‘speed-of-light’ wires  The time-domain solution is: In this case, A is a constant. Gamma, the propagation constant, provides information about the characteristics of this line. The imaginary part of gamma, denoted by beta, is inversely related to the phase velocity, and the real part of gamma, denoted by alpha, is the attenuation constant. R. Chang,Thesis, 2002.

7. 7 Nearly ‘speed-of-light’ wires LC dominated region RC region R. Chang,Thesis, 2002.

8. 8 Nearly ‘speed-of-light’ wires  Take advantage of the inductance-dominated high-frequency regime of on-chip interconnects  Peak phase velocity is speed of light in SiO 2  Reduce low-frequency spectral components of the signal which introduce ISI and lag LC dominated response Chang et al., JSSC, 2003.

9. 9 Outline  Scaling trends and motivation  Prior work on low-latency repeater-less links by exploiting transmission-line behavior  Negative-impedance converter (NIC)  System architecture  Transmitter design  Receiver design  Measurement results  Summary and conclusions  References

10. 10 Distributed Loss Compensation  Used in long-distance telephone network before the introduction of optics for long-haul communications  Clock distribution networks -Standing wave oscillators, [ O’ Mahony et al., JSSC 2003] -Rotary traveling-wave oscillator arrays, [Wood et al., JSSC 2001]  Distributed amplifiers use similar ideas to extend the unity- gain bandwidth

11. 11 Negative Impedance Converter  Pole ≈ -g m /(2C) ; zero ≈ 1/(2RC) Match frequency-dependent loss characteristics Jose et al., ISSCC, 2006.

12. 12 NIC Attenuation Compensation -  With NICs Without NICs Increasing R, C=50 fF Increasing R, C=600 fF  A larger cap C increases the amount of loss compensation at higher frequencies  Negative  leads to instability which can lead to excessive ringing or oscillations Jose et al., ISSCC, 2006.

13. 13 Latency Comparison  NIC links have lower latencies at higher widths due to transmission-line behavior of interconnects for widths > 2 µm  For very small widths (large R), the interconnect is predominantly in the RC domain Latency (ps) Width (µm) Length=14mm NIC Link Optimally buffered link Jose et al., ISSCC, 2006.

14. 14 Power Comparison  Power consumed increases rapidly for widths < 4µm due to the large number of NIC elements required  Increasing bit energy in the optimally repeated case is due to large number of repeaters needed to drive the additional C Energy (pJ/bit) Width (µm) Length=14mm NIC Link Optimally buffered link NIC Attenuation Compensation -  Jose et al., ISSCC, 2006.

15. 15 Outline  Scaling trends and motivation  Prior work on low-latency repeater-less links by exploiting transmission-line behavior  Negative-impedance converter (NIC)  System architecture  Transmitter design  Receiver design  Measurement results  Summary and conclusions  References

16. 16 Test-Chip Components  3-Gbps link in 0.18-µm technology with a 1.5-GHz system clock  17-bit LFSR for generating PRBS and an error counter for obtaining BER  Far-end and near-end waveforms obtained by pico-probing 5mm PLL 1.67mm SRAM LFSR Driver Receiver Serpentine serial link SRAM Error Counter Jose et al., ISSCC, 2006.

17. 17 System Architecture Data Bandwidth : 2 / clock period [bits/sec] Clock period : 1.5 GHz Jose et al., ISSCC, 2006.

18. 18 Transmitter Design  Driver consists of M1-2 and termination resistor R T  Predrivers use pseudo-nmos logic  I d sets the bias point of the NICs Jose et al., ISSCC, 2006.

19. 19  Modified StrongARM latch: Low-swing differential receiver Small aperture time for high data-rate  Line termination: N-well resistor with value of 2Z o Excessive capacitive loading at receiver inputs can introduce ISI Receiver Design Calibration Caps Calibration Caps 70 mV far-end swing Jose et al., ISSCC, 2006.

20. 20 Receiver Sampling-point Calibration  Calibration is performed at the receiver end  Clock skew compensation between transmitter and receiver  Link latency compensation Jose et al., ISSCC, 2006.

21. 21 Outline  Scaling trends and motivation  Prior work on low-latency repeater-less links by exploiting transmission-line behavior  Negative-impedance converter (NIC)  System architecture  Transmitter design  Receiver design  Measurement results  Summary and conclusions  References

22. 22 Measurement Results -    obtained from measured S-parameters  The NICs cause noticeable bandwidth reduction at frequencies beyond ≈ 9 GHz  The NICs contribute towards a significant reduction in  from ≈ 50 MHz to 7 GHz Jose et al., ISSCC, 2006.

23. 23 Measurement Results -    obtained from measured S-parameters  Phase velocity decreases (  increases) at high frequencies Jose et al., ISSCC, 2006.

24. 24 Outline  Prior work on low-latency repeater-less links by exploiting transmission-line behavior  Negative-impedance converter (NIC)  System architecture  Transmitter design  Receiver design  Measurement results  Summary and conclusions  References

25. 25 Summary Throughput3 Gbps Clock frequency 1.5 GHz Width/ Length 8 µm / 14 mm 0.3 µm / 14 mm 8 µm / 14 mm Link-latency12.1 ps/mm 55 ps/mm18.6 ps/mm Number of NICs/repeaters 7 185 Power consumed 0.16 pJ/bit/mm0.17 pJ/bit/mm 0.5 pJ/bit/mm Distributed loss compensation (DDR) Optimally repeated link (DDR) Optimally repeated link (DDR) Jose et al., ISSCC, 2006.

26. 26 Conclusions  As technology scales, on-chip latencies are increasingly becoming a bottleneck for on-chip performance  Optimally repeated RC delays represent latencies that are as much as 3 X those determined by the speed of light in SiO 2  Repeaters consume a growing fraction of power and silicon area  Using distributed loss compensation with NICs leads to arbitrarily long links with a significant latency and energy/bit/mm advantage over optimally repeated RC links

27. 27 References A. P. Jose and K. L. Shepard, “Distributed Loss Compensation for Low- latency On-chip Interconnects,” IEEE International Solid-State Circuits Conference, 2006. A. P. Jose, G. Patounakis and K. L. Shepard, “Near Speed-of-light Onchip Interconnects using Pulsed Current-mode Signaling,” Symp. VLSI Circuits, June, 2005. R. T. Chang, et al, “Near speed-of-light signaling over on-chip electrical interconnects,” IEEE J. Solid-State Circuits, vol. 38, no. 5, May, 2003. R. Chang, “ Near Speed-of-Light On-Chip Electrical Interconnects,” A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY, November 2002.