1. 1 TM The ARM Architecture - 1 Embedded Systems Lab./Honam University ARM Architecture SA-110 ARM7TDMI 4T 1 Halfword and signed halfword / byte support System mode Thumb instruction set 2 4 ARM9TDMI SA-1110 ARM720TARM940T Improved ARM/Thumb Interworking CLZ 5TE Saturated maths DSP multiply- accumulate instructions XScale ARM1020E ARM9E-S ARM966E-S 3 Early ARM architectures ARM9EJ-S 5TEJ ARM7EJ-S ARM926EJ-S Jazelle Java bytecode execution 6 ARM1136EJ-S ARM1026EJ-S SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support

2. 2 TM The ARM Architecture - 2 Embedded Systems Lab./Honam University ARM10E Product Roadmap

3. 3 TM The ARM Architecture - 3 Embedded Systems Lab./Honam University ARM7TDMI

4. 4 TM The ARM Architecture - 4 Embedded Systems Lab./Honam University ARM9TDMI

5. 5 TM The ARM Architecture - 5 Embedded Systems Lab./Honam University SA-1110

6. 6 TM The ARM Architecture - 6 Embedded Systems Lab./Honam University ETM10C Interface

7. 7 TM The ARM Architecture - 7 Embedded Systems Lab./Honam University ARM920T

8. 8 TM The ARM Architecture - 8 Embedded Systems Lab./Honam University ARM Thumb - AT91F40816

9. 9 TM The ARM Architecture - 9 Embedded Systems Lab./Honam University LPC21xx

10. 10 TM The ARM Architecture - 10 Embedded Systems Lab./Honam University Bulverde

11. 11 TM The ARM Architecture - 11 Embedded Systems Lab./Honam University When an exception occurs, the core: Copies CPSR into SPSR_ Sets appropriate CPSR bits u If core implements ARM Architecture 4T and is currently in Thumb state, then n ARM state is entered. u Mode field bits u Interrupt disable flags if appropriate. Maps in appropriate banked registers Stores the “return address” in LR_ Sets PC to vector address To return, exception handler needs to: Restore CPSR from SPSR_ Restore PC from LR_ Exception Handling and the Vector Table

12. 12 TM The ARM Architecture - 12 Embedded Systems Lab./Honam University Intel ® IXA – The Next Generation Intel ® IXA characteristics: Definable: Intel ® IXA is Intel’s packet processing architecture focused on our network processors Measurable: Architectural core is the microengine technology + Intel ® XScale™ microarchitecture Lasting: Software portability across multiple product generations Micro-engineMicro-engine Intel ® XScale™ microarchitecture Intel ® IXA Network Processor + Intel® IXA portability framework Customer Applications Microengine technology Enables low power, high density processing Enables high-performance, programmable network processing Enables software portability

13. 13 TM T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D Embedded Systems Lab./Honam University

14. 14 TM T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D Embedded Systems Lab./Honam University

15. 15 TM The ARM Architecture - 15 Embedded Systems Lab./Honam University Optional 10Gbps SONET line card 10GbE OC-192c SPI I/F Fabric CSIX I/F RDR Packet Memory 10Gbs 15Gbs 10Gbs Control Plane Processor PCI 64/66 Fabric Interface Chip (FIC) SAR’ing Classification Metering Policing Initial Congestion Management Ingress Processor Traffic Shaping Flexible Choices diff serve TM 4.1 … Egress Processor Intel IXP2800 Egress Processor DRAMDRAMDRAMQ QQDRDRQQDRDRQ QQDRDRQQDRDRQ QQDRDRQQDRDR QDR SRAM Queues & Tables Q QQDRDRQQDRDR Intel IXP2800 Ingress Processor DRAMDRAMDRAM QDRQDRQ QQDRDRQQDRDR RDR Packet Memory QDR SRAM Queues & Tables Q QQDRDRQQDRDR 10 GbE WAN / PPP/ ATM/ OTN / SONET/ SDH CDR, DEMUX CDR, DEMUX Flow Ctl TCAM TCAM 000

16. 16 TM The ARM Architecture - 16 Embedded Systems Lab./Honam University Optional 10Port 1Gbps Ethernet line card 10x1GbE SPI I/F Fabric CSIX I/F RDR Packet Memory 10Gbs 15Gbs 10Gbs PCI 64/66 SAR’ing Classification Metering Policing Initial Congestion Management Ingress Processor Traffic Shaping Flexible Choices diff serve TM 4.1 … Egress Processor Intel IXP2800 Egress Processor DRAMDRAMDRAMQ QQDRDRQQDRDRQ QQDRDRQQDRDRQ QQDRDRQQDRDR QDR SRAM Queues & Tables Q QQDRDRQQDRDR Intel IXP2800 Ingress Processor DRAMDRAMDRAM QDRQDRQ QQDRDRQQDRDR RDR Packet Memory QDR SRAM Queues & Tables Q QQDRDRQQDRDR 10 x 1 GbE LAN Control Plane Processor Flow Ctl Fabric Interface Chip (FIC) TCAMTCAM 000

17. 17 TM The ARM Architecture - 17 Embedded Systems Lab./Honam University Optional 10Gbs Ethernet to SONET card 10GbE 10x1Gb SPI I/F OC-192 4xOC48 SPI I/F QDR SRAM Queues & Tables 10Gbs PCI 64/66 Server or Disk Farms MetroOrWAN Intel IXP2800 Egress Processor DRAMDRAMDRAMQ QQDRDRQQDRDRQ QQDRDRQQDRDRQ QQDRDRQQDRDRQ QQDRDRQQDRDR Intel IXP2800 Ingress Processor DRAMDRAMDRAM QDRQDRQ QQDRDRQQDRDRQ QQDRDRQQDRDR RDR Packet Memory QDR SRAM Queues & Tables RDR Packet Memory Control Plane Processor Flow Ctl TCAM TCAM 000