1. ECE 260B – CSE 241A Partitioning & Floorplanning 1http://vlsicad.ucsd.edu ECE260B – CSE241A Winter 2005 Partitioning & Floorplanning Website: http://vlsicad.ucsd.edu/courses/ece260b-w05

2. ECE 260B – CSE 241A Partitioning & Floorplanning 2http://vlsicad.ucsd.edu Key Design Stages  Synthesis  Partitioning  Floorplanning  Power/ground Generation  Clock Generation  Placement  Routing

3. ECE 260B – CSE 241A Partitioning & Floorplanning 3http://vlsicad.ucsd.edu Floorplanning

4. ECE 260B – CSE 241A Partitioning & Floorplanning 4http://vlsicad.ucsd.edu Floorplanning Input  Design netlist (required)  Area requirements (required)  Power requirements (required)  Timing constraints (required)  Physical partitioning information (required)  Die size vs. performance vs. schedule trade-off (required)  I/O placement (optional)  Macro placement information (optional)

5. ECE 260B – CSE 241A Partitioning & Floorplanning 5http://vlsicad.ucsd.edu Floorplanning Output  Die/block area  I/Os placed  Macros placed  Power grid designed  Power pre-routing  Standard cell placement areas  Design ready for standard cell placement

6. ECE 260B – CSE 241A Partitioning & Floorplanning 6http://vlsicad.ucsd.edu Floorplanning Output

7. ECE 260B – CSE 241A Partitioning & Floorplanning 7http://vlsicad.ucsd.edu Floorplan data path RAM std cell blocks I/O pads Routing channels  Blocks inside a pad frame  Routing inside, between blocks  Different-sized blocks more difficult than standard cells to place and route  Blocks l Hard, soft, semi-soft l Rectangular, L-shaped, T-shaped, rectilinear l Can rotate, mirror, … Courtesy K. Yang, UCLA

8. ECE 260B – CSE 241A Partitioning & Floorplanning 8http://vlsicad.ucsd.edu Design Styles  Full Customized l Analog / RF l CPU design  ASIC (Application Specific IC) l Gate array / sea of gate / standard cells l Via programmable l Structured ASICs  Programmable Logics l PLA l FPGA  Software implementation l Micro-code Courtesy K. Yang, UCLA

9. ECE 260B – CSE 241A Partitioning & Floorplanning 9http://vlsicad.ucsd.edu Size Estimation  Why we care: l If area is too small: P&R will not finish or meet timing, will run too long l Schedule and die size inversely related l Performance and die size have complex relationship  Rule of thumb (must correct for power, clock, etc.): -3LM: Cell utilization 65 percent // what is utilization? -4LM: Cell utilization 70 percent -5LM: Cell utilization 75 percent -6LM: Cell utilization 80 percent  Floorplan metrics l Low interconnect density  Cell util (standard cell area/standard cell row area) l High interconnect density  “Net util” (number of nets/standard cell area) Die size Physical Design Schedule Perf Die size

10. ECE 260B – CSE 241A Partitioning & Floorplanning 10http://vlsicad.ucsd.edu Channels  Channels end at block boundaries  Alternate channel definitions possible, depending on position of blocks A BC channel 1 ch 2 ch 1ch 2 ch 3 A BC A B C Courtesy K. Yang, UCLA

11. ECE 260B – CSE 241A Partitioning & Floorplanning 11http://vlsicad.ucsd.edu Channel Intersection Graph  Nodes are channels, edges correspond to pairs of channels that touch  Channel graph shows paths between channels  Channel graph can be used to guide global routing A B C D E Courtesy K. Yang, UCLA

12. ECE 260B – CSE 241A Partitioning & Floorplanning 12http://vlsicad.ucsd.edu Channel Ordering  Wire out end of one channel creates pin on side of next channel  “Wheel” = Circular constraints that create an unroutable configuration of channels channel A channel B constraint A B C D Courtesy K. Yang, UCLA

13. ECE 260B – CSE 241A Partitioning & Floorplanning 13http://vlsicad.ucsd.edu Slicing Floorplan Represented by Binary Tree  A slicing floorplan can be recursively cut in two without cutting any blocks  A slicing floorplan is guaranteed to have no “wheels”, therefore guaranteed to have a feasible order of routing for the channels  A slicing floorplan can be represented as a binary tree, with internal nodes representing slices in the floorplan and leaves representing blocks. Courtesy K. Yang, UCLA A B C D E 1 2 3 4 1 23 4 AB C DE

14. ECE 260B – CSE 241A Partitioning & Floorplanning 14http://vlsicad.ucsd.edu O-Tree  Partial ordering based on projection overlapping (with given physical locations)  Transforming into binary trees by pivoting, etc.  Coded in a node sequence given a tree traversal algorithm l E.g., OACBDEF for DFS  Condensed solution space B C D E F Courtesy K. Yang, UCLA A O

15. ECE 260B – CSE 241A Partitioning & Floorplanning 15http://vlsicad.ucsd.edu Sequence Pair  Based on layout partitions by non- overlapping ascending/descending staircases  Coded in two node sequences l E.g., CEDFAB for descending staircases and l ABCDEF for ascending staircases  Larger solution space, finer representation B C D E F Courtesy K. Yang, UCLA A

16. ECE 260B – CSE 241A Partitioning & Floorplanning 16http://vlsicad.ucsd.edu Partitioning

17. ECE 260B – CSE 241A Partitioning & Floorplanning 17http://vlsicad.ucsd.edu Outline  Introduction  Kernighan-Lin Algorithm  Fiduccia-Mattheyses Algorithm  Partitioning by Network Flow  Clustering  End-case Partitioning (and Placement)

18. ECE 260B – CSE 241A Partitioning & Floorplanning 18http://vlsicad.ucsd.edu Partitioning  Decomposition of a complex system into smaller subsystems l Done hierarchically l Partitioning done until each subsystem has manageable size l Each subsystem can be designed independently  Interconnections between partitions minimized l Less hassle interfacing the subsystems l Communication between subsystems usually costly l Time-budgeting

19. ECE 260B – CSE 241A Partitioning & Floorplanning 19http://vlsicad.ucsd.edu Example: Partitioning of a Circuit Input size: 48 Cut 1=4 Size 1=15 Cut 2=4 Size 2=16Size 3=17

20. ECE 260B – CSE 241A Partitioning & Floorplanning 20http://vlsicad.ucsd.edu Hierarchical Partitioning  Levels of partitioning: l System-level partitioning: Each sub-system can be designed as a single PCB l Board-level partitioning: Circuit assigned to a PCB is partitioned into sub-circuits each fabricated as a VLSI chip l Chip-level partitioning: Circuit assigned to the chip is divided into manageable sub- circuits NOTE: physically not necessary

21. ECE 260B – CSE 241A Partitioning & Floorplanning 21http://vlsicad.ucsd.edu Delay at Different Levels of Partitions A B C PCB1 D x 10x 20x PCB2

22. ECE 260B – CSE 241A Partitioning & Floorplanning 22http://vlsicad.ucsd.edu Partitioning: Formal Definition  Input: l Graph or hypergraph l Usually with vertex weights l Usually weighted edges  Constraints l Number of partitions (K-way partitioning) l Maximum capacity of each partition OR maximum allowable difference between partitions  Objective l Assign nodes to partitions subject to constraints s.t. the cutsize is minimized  Tractability l Is NP-complete 

23. ECE 260B – CSE 241A Partitioning & Floorplanning 23http://vlsicad.ucsd.edu Hypergraphs in VLSI CAD  Circuit netlist represented by hypergraph Slides Courtesy Kia Bazargan, U. Minn

24. ECE 260B – CSE 241A Partitioning & Floorplanning 24http://vlsicad.ucsd.edu Hypergraph Partitioning in VLSI  Variants l directed/undirected hypergraphs l weighted/unweighted vertices, edges l constraints, objectives, …  Human-designed instances  Benchmarks l up to 4,000,000 vertices l sparse (vertex degree » 4, hyperedge size » 4) l small number of very large hyperedges  Efficiency, flexibility: KL-FM style preferred

25. ECE 260B – CSE 241A Partitioning & Floorplanning 25http://vlsicad.ucsd.edu Some Notations  A net n is cut by a cluster C if at least one, but not all, pins of n is in C.  We use E(C) to denote the set of nets cut by a cluster C.  We use E(P) to denote the set of nets cut by at least one cluster of a partition P.  We use w(C) to denote the no. of cells assigned to a cluster C.

26. ECE 260B – CSE 241A Partitioning & Floorplanning 26http://vlsicad.ucsd.edu Some Bipartitioning Formulations  Min-Cut Bipartitioning: l Objective : Minimize F(P 2 ) = |E(C 1 )| = |E(C 2 )|  Min-Cut Bisection: l Objective : Minimize F(P 2 ) = |E(C 1 )| = |E(C 2 )| l Constraint : |w(C 1 ) - w(C 2 )|    Size-Constrained Min-Cut Bipartitioning: l Objective : Minimize F(P 2 ) = |E(C 1 )| = |E(C 2 )| l Constraint: L  w(C 1 ), w(C 2 )  U  Minimum Ratio Cut Bipartitioning: l Objective : Minimize F(P 2 ) = |E(C 1 )|/(w(C 1 )  w(C 2 ))

27. ECE 260B – CSE 241A Partitioning & Floorplanning 27http://vlsicad.ucsd.edu Some Multi-Way Partitioning Formulations  Size-Constrained Min-Cut k-Way Partitioning: l Objective : Minimize F(P k ) l Constraint: L  w(C i )  U  C i  P k  Many other complicated formulations  k-way partitioning: Formulation Given a netlist of n cells V = {v 1, v 2, …, v n }, assign the cells to k clusters P k = {C 1, C 2, …, C k } satisfying some given constraints such that an objective function F(P k ) is optimized. Partitioning: k is small O(1) Clustering: k is large O(n) Technology Mapping: Constraints on the clusters

28. ECE 260B – CSE 241A Partitioning & Floorplanning 28http://vlsicad.ucsd.edu Outline  Introduction  Kernighan-Lin Algorithm  Fiduccia-Mattheyses Algorithm  Partitioning by Network Flow  Clustering  End-case Partitioning (and Placement)

29. ECE 260B – CSE 241A Partitioning & Floorplanning 29http://vlsicad.ucsd.edu Kernighan-Lin (KL) Algorithm  On non-weighted graphs  An iterative improvement technique  A two-way (bisection) partitioning algorithm  The partitions must be balanced (of equal size)  Iterate as long as the cutsize improves: l Find a pair of vertices that result in the largest decrease in cutsize if exchanged l Exchange the two vertices (potential move) l “Lock” the vertices l If no improvement possible, and still some vertices unlocked, then exchange vertices that result in smallest increase in cutsize W. Kernighan and S. Lin, Bell System Technical Journal, 1970.

30. ECE 260B – CSE 241A Partitioning & Floorplanning 30http://vlsicad.ucsd.edu Kernighan-Lin (KL) Algorithm  Initialize l Bipartition G into V 1 and V 2, s.t., |V 1 | = |V 2 |  1 l n = |V|  Repeat l for i=1 to n/2 -Find a pair of unlocked vertices v ai  V 1 and v bi  V 2 whose exchange makes the largest decrease or smallest increase in cut-cost -Mark v ai and v bi as locked -Store the gain gi. l Find k, s.t.  i=1..k g i =Gain k is maximized l If Gain k > 0 then move v a1,...,v ak from V 1 to V 2 and v b1,...,v bk from V 2 to V 1.  Until Gain k  0

31. ECE 260B – CSE 241A Partitioning & Floorplanning 31http://vlsicad.ucsd.edu An Example abcd a b c d 0123 1014 2103 3430 a bd c 1 2 3 1 4 3 Slides courtesy F. Y. Young, U. Hong Kong

32. ECE 260B – CSE 241A Partitioning & Floorplanning 32http://vlsicad.ucsd.edu An Example - Pass One a bd c 1 2 3 1 4 3 g(a,c) = -1+3-3+1 = 0 g(a,d) = -1+2-3+4 = 2 g(b,c) = -1+4-3+2 = 2 g(b,d) = -1+1-3+3 = 0 g 1 = 2 d ba c 4 3 3 1 1 2 g(b,c) = -4+1-2+3 = -2 g 2 = -2 d ca b 3 4 3 1 2 1  G = g 1 = 2 (k = 1)

33. ECE 260B – CSE 241A Partitioning & Floorplanning 33http://vlsicad.ucsd.edu An Example - Pass Two d ba c 4 3 3 1 1 2 g(a,b) = -2+3-4+1 = -2 g(a,d) = -2+1-4+3 = -2 g(c,b) = -2+3-4+1 = -2 g(c,d) = -2+1-4+3 = -2 g 1 = -2 b g(a,b) = -3+2-1+4 = 2 g 2 = 2 G = g 1 + g 2 = 0 (k = 2) STOP! a d c 1 3 42 31 d c a b 1 3 3 1 42

34. ECE 260B – CSE 241A Partitioning & Floorplanning 34http://vlsicad.ucsd.edu Cut During One Pass (Bipartitioning) Moves Cut

35. ECE 260B – CSE 241A Partitioning & Floorplanning 35http://vlsicad.ucsd.edu Kernighan-Lin (KL) : Analysis  Time complexity? l Inner (for) loop -Iterates n/2 times -Iteration 1: (n/2) x (n/2) -Iteration i: (n/2 – i + 1) (n/2 – i + 1). l Passes? Usually independent of n l O(n 3 )  Drawbacks? l Local optimum l Balanced partitions only l No weight for the vertices l High time complexity l Only on edges, not hyper-edges

36. ECE 260B – CSE 241A Partitioning & Floorplanning 36http://vlsicad.ucsd.edu Outline  Introduction  Kernighan-Lin Algorithm  Fiduccia-Mattheyses Algorithm  Partitioning by Network Flow  Clustering  End-case Partitioning (and Placement)

37. ECE 260B – CSE 241A Partitioning & Floorplanning 37http://vlsicad.ucsd.edu Fiduccia-Mattheyses Algorithm: Basic Ideas  Differences from KL: l Move only one cell each time. l Cells can have different sizes. l Nets can be multi-terminal. l Maintain a balanced partition after every move.

38. ECE 260B – CSE 241A Partitioning & Floorplanning 38http://vlsicad.ucsd.edu FM Algorithm  Start with a balanced partition P = {X,Y}.  Repeat l For i = 1 to n: -Choose a free cell b  X  Y s.t. moving b to the other side gives the highest gain, gain(b), and moving b preserves balance in P. -Move and lock b. -Let gi = gain(b). l Find k s.t. G = g1 + g2 + ….. + gk is maximized and shuffle the cells up to this kth step.  Until G = 0.

39. ECE 260B – CSE 241A Partitioning & Floorplanning 39http://vlsicad.ucsd.edu An Example abcabc defdef acac defdef b locked acac dfdf be acac f b e d g1g1 g2g2 g3g3 g4g4

40. ECE 260B – CSE 241A Partitioning & Floorplanning 40http://vlsicad.ucsd.edu An Example c f b e d g5g5 a f b e d g6g6 a c b e d a cf If G = g 1 + g 2 + g 3 + g 4 is the largest partial sum, the partition after this pass is: cdecde afbafb

41. ECE 260B – CSE 241A Partitioning & Floorplanning 41http://vlsicad.ucsd.edu Balanced Partition  A partition P = (X,Y) is balanced iff: for some constant r  1 where w(X) is the total size of the cells in X. To preserve balance, a cell b is moved in a pass only if: after moving b where W = w(X  Y) and Smax is the maximum cell size

42. ECE 260B – CSE 241A Partitioning & Floorplanning 42http://vlsicad.ucsd.edu KL and FM Extensions: Tie-Breaking Strategy  When picking the highest gain move, break ties by looking ahead a certain number of steps.  If ties still occur, some researchers observe that LIFO order improves solution quality.

43. ECE 260B – CSE 241A Partitioning & Floorplanning 43http://vlsicad.ucsd.edu Ratio of #edges to #vertices  Solution quality of KL and FM depends on the ratio of #edges to #vertices: good if ratio > 5 and bad if ratio < 3. VLSI circuits have ratio 1.8-2.5 typically.  Goldberg and Burstein suggested contracting edges to increase the ratio: AB AB

44. ECE 260B – CSE 241A Partitioning & Floorplanning 44http://vlsicad.ucsd.edu Outline  Introduction  Kernighan-Lin Algorithm  Fiduccia-Mattheyses Algorithm  Partitioning by Network Flow  Clustering  End-case Partitioning (and Placement)

45. ECE 260B – CSE 241A Partitioning & Floorplanning 45http://vlsicad.ucsd.edu Network Flow Technique st a b cd 16 13 10497 12 20 4 11 st a b cd 11/16 12/13 101/497/7 12/12 19/20 4/4 11/11 min-cut = max-flow  The network flow technique can find the min-cut bipartition optimally, but not necessarily balanced.  Apply the algorithm repeatedly to obtain a balanced bipartition.

46. ECE 260B – CSE 241A Partitioning & Floorplanning 46http://vlsicad.ucsd.edu Network Flow Technique  The network flow technique is very useful in many different research areas.  Many sophisticated improvements have been made to the original algorithm.  Ford & Fulkerson: O(|E||f|) where |f| is the size of the total flow. Note that for unit capacity, |f|  |E|, so O(|E| 2 ) time.

47. ECE 260B – CSE 241A Partitioning & Floorplanning 47http://vlsicad.ucsd.edu Circuit Partitioning  We can apply the network flow algorithm in partitioning circuits.  The biggest problem is that the two partitions may not be balanced.  The problem of obtaining two balanced partitions with minimum cut is NP-complete.  However we can apply some heuristics to balance the two partitions.

48. ECE 260B – CSE 241A Partitioning & Floorplanning 48http://vlsicad.ucsd.edu Flow-Balanced-Bipartition (FBB)  Find a min-cut C = (X,Y) in the network N  If (1-  )W/2  w(X)  (1+  )W/2, stop and return C  If w(X) < (1-  )W/2 then l Collapse all nodes in X to s l Collapse to s a node v  Y incident on a net in C l Go to to step 1  If w(X) > (1+  )W/2 … (similarly)... Why do we need this step?

49. ECE 260B – CSE 241A Partitioning & Floorplanning 49http://vlsicad.ucsd.edu Circuit Representation  Another problem in applying the network flow technique in circuit partitioning is how to represent a circuit correctly by a graph. ABCD How to represent this netlist by a simple graph?

50. ECE 260B – CSE 241A Partitioning & Floorplanning 50http://vlsicad.ucsd.edu Hypergraph ABCD H(V,E) where V = {A, B, C, D} E = {n 1, n 2, n 3 } n 1 = {A, B, C, D} n 2 = {A, B} n 3 = {C, D} In hypergraph, an edge is a set of vertices. Circuits can be represented by hypergraphs, but the net- work flow method can only be used in simple graphs.

51. ECE 260B – CSE 241A Partitioning & Floorplanning 51http://vlsicad.ucsd.edu Weighted Undirected Graph Use a clique to model a net: ABCD What should be the edge weights? “A proper model for the partitioning of electrical circuits”, Schweikert and Kernighan, DAC, 1972.

52. ECE 260B – CSE 241A Partitioning & Floorplanning 52http://vlsicad.ucsd.edu Weighted Undirected Graph ABCD 1/4 1/2 Cut size = 4*1/4 = 1 (Actual cut size = 1) Cut size = 3*1/4+1/2 = 5/4 (Actual cut size = 2) edge weight = n(k) = no. of cells in net k

53. ECE 260B – CSE 241A Partitioning & Floorplanning 53http://vlsicad.ucsd.edu Weighted Undirected Graph ABCD 1/3 11 Cut size = 4*1/3 = 4/3 (Actual cut size = 1) Cut size = 3*1/3+1 = 2 (Actual cut size = 2) edge weight =

54. ECE 260B – CSE 241A Partitioning & Floorplanning 54http://vlsicad.ucsd.edu Circuit Representation  It is proved that exact modeling of a hypergraph by a graph with positive weights is impossible. [Ihler, Wagner & Wager, 1993]  However, we can model a hypergraph H by a simple graph G such that when we apply the network flow algorithm, the min-cut in G is equal to the min-cut in H.

55. ECE 260B – CSE 241A Partitioning & Floorplanning 55http://vlsicad.ucsd.edu Weighted Directed Graph A B C A B C       1 What will happen when we apply the max-flow min-cut algorithm to the graph G? Original circuit C: G:G:

56. ECE 260B – CSE 241A Partitioning & Floorplanning 56http://vlsicad.ucsd.edu Weighted Directed Graph ABCD    1     1         1

57. ECE 260B – CSE 241A Partitioning & Floorplanning 57http://vlsicad.ucsd.edu Modeling a Circuit d a b c e f g d s b c e f t C:C:G:G:

58. ECE 260B – CSE 241A Partitioning & Floorplanning 58http://vlsicad.ucsd.edu Modeling a Circuit  Lemma: If C has a cut (X,Y) of size K, G has a cut (X’,Y’) of size K. If G has a cut (X’,Y’) of size K, C has a cut (X,Y) of size less than or equal to K  Corollary: If (X’,Y’) is the min-cut of G of size K, the corresponding cut (X,Y) in C is also a min-cut of C of size K  Let G = (V ’,E ’ ) be the flow network modeling the circuit C = (V,E): A B C       1 C:G: A B C |V’| = ? |E’| = ?

59. ECE 260B – CSE 241A Partitioning & Floorplanning 59http://vlsicad.ucsd.edu Efficient Implementation  Repeatedly computing max-flow is time consuming. No need to compute max-flow from scratch in every iteration.  Retain the flow function computed in the previous iteration. Find additional flow to saturate the bridging edges from one iteration to another.  Total time taken for all the iterations is O(|E’||V’|).

60. ECE 260B – CSE 241A Partitioning & Floorplanning 60http://vlsicad.ucsd.edu Outline  Introduction  Kernighan-Lin Algorithm  Fiduccia-Mattheyses Algorithm  Partitioning by Network Flow  Clustering  End-case Partitioning (and Placement)

61. ECE 260B – CSE 241A Partitioning & Floorplanning 61http://vlsicad.ucsd.edu Clustering  Clustering l Bottom-up process l Merge heavily connected components into clusters l Each cluster will be a new “node” l “Hide” internal connections (i.e., connecting nodes within a cluster) l “Merge” two edges incident to an external vertex, connecting it to two nodes in a cluster  Can be a preprocessing step before partitioning l Each cluster treated as a single node 3 4 16 25 6 4 3 1 1 1 3 4 6 1,2 5 4 3 1 2 3,4 6 1,2 5 3 1 2

62. ECE 260B – CSE 241A Partitioning & Floorplanning 62http://vlsicad.ucsd.edu Ratio Cut Objective  It is not desirable to have a pre-defined ratio on the partition sizes.  Wei and Cheng proposed the ratio cut objective ( C XY /(|X|  |Y|) where C XY is the cut size ). Try to locate natural clusters in the circuit.  A heuristic based on FM was proposed.

63. ECE 260B – CSE 241A Partitioning & Floorplanning 63http://vlsicad.ucsd.edu Multi-Level Partitioning Clustering Applying FM Unclustering Refining by FM

64. ECE 260B – CSE 241A Partitioning & Floorplanning 64http://vlsicad.ucsd.edu hMETIS  Freely available at http://www-users.cs.umn.edu/~karypis/metis/hmetis/  Extension of METIS graph hierarchical partitioning tool l Coarsening phase l Refinement phase  See also UCLA MLPart http://vlsicad.ucsd.edu/GSRC/Slots/Partitioning/MLPart/ initial hypergraph coarsening phase refinement phase projected partition refined partition random partition

65. ECE 260B – CSE 241A Partitioning & Floorplanning 65http://vlsicad.ucsd.edu Coarsening  Goal: create a smaller hypergraph such that a good bisection is not significantly than one on the original  How to select the vertices to condense? l edge coarsening -best matching pairs of hyperedge vertices are collapsed l hyperedge coarsening -independent set of hyperedges are collapsed -preference given to maximum weights and small sizes l modified hyperedge coarsening -hyperedge coarsening followed by collapse of the remaining vertices that do not belong to another hyperedge

66. ECE 260B – CSE 241A Partitioning & Floorplanning 66http://vlsicad.ucsd.edu Coarsening (cont’d) edge coarseninghyperedge coarsening modified hyperedge coarsening 3 hyperedges 12 vertices 5.3 pins / hyperedge 3 hyperedges 6 vertices 3.3 pins / hyperedge 1 hyperedge 5 vertices 5 pins / hyperedge 1 hyperedge 3 vertices 3 pins / hyperedge

67. ECE 260B – CSE 241A Partitioning & Floorplanning 67http://vlsicad.ucsd.edu Uncoarsening  Initial partition is a balanced random bisection  Partition is refined at this level l Fiduccia-Mattheyses (FM-EE) -constrained to only two passes -each pass is stopped after k zero-gain moves (early-exit) -Hyperedge Refinement (HER) –entire hyperedges are moved across the cut  Projection of cut onto more complete hypergraph

68. ECE 260B – CSE 241A Partitioning & Floorplanning 68http://vlsicad.ucsd.edu Outline  Introduction  Kernighan-Lin Algorithm  Fiduccia-Mattheyses Algorithm  Partitioning by Network Flow  Clustering  End-case Partitioning (and Placement)