1. Chapter 2-2 Assembly Instructions Number Systems Number Systems Assembly Instructions Assembly Instructions Branch Branch Next Lecture Next Lecture  Addressing Modes  Stacks and Queues  Subroutines

2. 2 Decimal to Binary Convert 85.8125 10 to binary Convert 85.8125 10 to binary

3. 3 2’s Complement Addition (± A) + (± B) If signs are different, simply add them If signs are different, simply add them  Discard carry if any, no overflow If signs are the same, add them If signs are the same, add them  If the sign bit is changed (i.e., overflow)  Compensate  Use higher precision (e.g., double)

4. 4 Calculations with signed 4-bits using 2’s complement Calculations with signed 4-bits using 2’s complement 6-33-6 6-33-6 (-3)+(-6)3+6 (-3)+(-6)3+6

5. 5 Signed magnitude, 1 ’ s complement and 2 ’ s complement Signed magnitude, 1 ’ s complement and 2 ’ s complement In 1 ’ s and 2 ’ s complement, the representation of the positive numbers is the same as in the sign and magnitude scheme. In 1 ’ s and 2 ’ s complement, the representation of the positive numbers is the same as in the sign and magnitude scheme. The three schemes differ in the way in which negative numbers are represented. The three schemes differ in the way in which negative numbers are represented. In all three schemes, the leftmost bit is 0 for positive numbers and 1 for negative numbers In all three schemes, the leftmost bit is 0 for positive numbers and 1 for negative numbers The choice of the number representation scheme has a direct influence on how easily arithmetic operations can be performed. The choice of the number representation scheme has a direct influence on how easily arithmetic operations can be performed. The 2 ’ s complement is the most suitable choice and it is used in all modern computers. The 2 ’ s complement is the most suitable choice and it is used in all modern computers. Binary Number Representations

6. 6 Memory locations, Addresses and Encoding Main memory is organized so that a group of n bits can be stored or retrieved in a single basic operation. Main memory is organized so that a group of n bits can be stored or retrieved in a single basic operation. Each group of 8 bits is called a byte Each group of 8 bits is called a byte Each group of n bits is called a word (16, 32 or 64 bits). Each group of n bits is called a word (16, 32 or 64 bits). Accessing a single word (or byte for byte addressable machines) in memory requires distinct addresses for each location. Accessing a single word (or byte for byte addressable machines) in memory requires distinct addresses for each location. Addresses usually vary from 0 to 2 k -1 (k: the number of address bits). Addresses usually vary from 0 to 2 k -1 (k: the number of address bits). The 2 k addresses constitute the address space. The 2 k addresses constitute the address space.

7. 7 Simple Sign and Magnitude Representation For a 32 bit number sign = b 31 magnitude = b 30 x 2 30 +…..+b 1 x 2 1 +b 0 x 2 0 1 for negative numbers = 0 for positive numbers

8. 8 How Are Characters Stored? Characters can be letters of the alphabet, decimal digits, punctuation marks … Characters can be letters of the alphabet, decimal digits, punctuation marks … Characters are represented by codes (6 to 8 bits long) Characters are represented by codes (6 to 8 bits long) 4 characters in the ASCII can be stored in a 32-bit word. 4 characters in the ASCII can be stored in a 32-bit word. ASCII: American Standard Code for Information Interchange

9. 9 Placing Bytes within a Word For byte addressable machines Big Endean: byte 0 is the leftmost byte of word 0   high byte - low memory address   e.g., used in some Motorola processors, e.g., 68000 Little Endean: byte 0 is the rightmost byte of word 0   high byte - high memory address   e.g., used in Intel processors AddressAddress

10. 10 Big and Little Endian - Example 0x12345678 0x90abcdef 1234567890abcdef +0+1+2+3 Address0 4 Address0 4 1234567890abcdef +3+2+1+0 Address0 4 Data in 32 bits Big Endian Little Endian Word

11. 11 What Do Instructions (i.e., Commands) Do A computer must have instructions capable of performing four types of operations A computer must have instructions capable of performing four types of operations  Data transfers between the main memory and the CPU registers  Ex: Move LocA,R1  Arithmetic and logic operations on data  Ex: Add R1,R2  Program sequencing and control  Ex: Jmp Loop  I/O transfers  Ex: In LocA

12. 12 Design Consideration for Instructions (ISA) Performance Performance  As efficient and fast as possible Fixed length vs. Variable length Fixed length vs. Variable length  ARM or IA32 Pipelining: boost performance Pipelining: boost performance  Pipeline-friendly RISC vs. CISC RISC vs. CISC  RISC: reduced instruction set computer  Fewer instructions (easier design of the control circuitry, enabling better pipelining)  CISC: complex instruction set computer  Many instructions (compact code size)

13. 13 Convention and Notation R1  [LOC] R1  [LOC]  contents of memory location LOC are transferred into register R1 C  [A]+[B] C  [A]+[B]  contents of memory locations A and B are fetched from the main memory and transferred into the CPU, where the sum of the two numbers is computed. The result is then in memory location C

14. 14 How Are Instructions Coded? A word can be used to represent an instruction A word can be used to represent an instruction Part of the word specifies the operation to be performed (opcode field) Part of the word specifies the operation to be performed (opcode field) An 8 bit opcode field can be encoded up to 256 different instructions An 8 bit opcode field can be encoded up to 256 different instructions The rest is reserved for the addressing modes. The rest is reserved for the addressing modes.  Addressing modes: different ways in which operands can be accessed

15. 15 Instruction Example for MIPS ISA Formats: rs: first source, rt: second source, rd: destination shamt: shift amount, funct: function Formats: rs: first source, rt: second source, rd: destination shamt: shift amount, funct: function op rs rt rdshamtfunct op rs rt 16 bit constant/address op 26 bit address R-type I-type J-type 6bits[31-26] 5bits[25-21] 5bits[20-16] 5bits[15-11] 5bits[10-6] 6bits[5-0]

16. 16 Instructions do not always have a length of one word Instructions do not always have a length of one word It is convenient to have the possibility of specifying operands that are shorter or longer than one word It is convenient to have the possibility of specifying operands that are shorter or longer than one word An operand length of 8 bit (one byte) is convenient because it is the size used to encode characters An operand length of 8 bit (one byte) is convenient because it is the size used to encode characters To enable access to the individual bytes, the smallest addressable unit in most computers is a byte (byte addressable computers) To enable access to the individual bytes, the smallest addressable unit in most computers is a byte (byte addressable computers) Instructions

17. 17 Instruction Sequencing Executing an Instruction Is a Two Phase Procedure Executing an Instruction Is a Two Phase Procedure  Instruction fetch: the instruction is fetched from the main memory and placed in the IR  Instruction execution: the instruction in the IR is examined to determine which operation to be performed. The specific operation is then performed by the CPU Sometime during the two phase procedure, the contents of the PC are incremented to point to the next instruction Sometime during the two phase procedure, the contents of the PC are incremented to point to the next instruction

18. 18 Block Diagram of a Processor

19. 19 Types of Instructions One operand One operand  Inc R1 Two Operands Two Operands  Move C,R1 Three Operands Three Operands  Add R1,R2,R3 Zero Operand Zero Operand  Ret

20. 20 Three Operand Instructions Instruction that contains three addressing mode fields, each pointing to one of the operands Instruction that contains three addressing mode fields, each pointing to one of the operands Such instructions can be represented symbolically as Such instructions can be represented symbolically as  Operation Source1, Source2, Destination Add A,B,C Operands A and B are the source, operand C is the destination Operands A and B are the source, operand C is the destination There are several computers, such as the PowerPC, in which the order of the source and destination is reversed. For example, the three operand instruction is written in the form There are several computers, such as the PowerPC, in which the order of the source and destination is reversed. For example, the three operand instruction is written in the form  Operation Destination, Source1, Source2

21. 21 Two operand instructions Format: Operation Source, Destination Format: Operation Source, Destination Example that performs the operation B  [A] +[B] Example that performs the operation B  [A] +[B] Add A,B The second operand is both a source and a destination The second operand is both a source and a destination A single two address instruction cannot be used to perform the original addition (Add A,B,C) without destroying neither A or B A single two address instruction cannot be used to perform the original addition (Add A,B,C) without destroying neither A or B Using two instructions: Using two instructions: Move B,C Move B,C Add A,C Add A,C

22. 22 One operand instructions Make use of an implicit operand called the accumulator Make use of an implicit operand called the accumulator Add A: adds the contents of memory location A to the contents of the accumulator and place the sum into the accumulator Add A: adds the contents of memory location A to the contents of the accumulator and place the sum into the accumulator Load A: copies the content of memory location A into the accumulator Load A: copies the content of memory location A into the accumulator Store A: stores the content of the accumulator into memory location A Store A: stores the content of the accumulator into memory location A Using one address instruction, the add operation C  [A] +[B] can be performed as follows Load A Add B Store C

23. 23 Zero operand instruction It is possible to use instructions in which the locations of all operands is defined implicitly It is possible to use instructions in which the locations of all operands is defined implicitly These instructions are found in machines that store the operands in a structure called pushdown stack These instructions are found in machines that store the operands in a structure called pushdown stack  PUSHA: push all registers into the stack

24. 24 Computers usually have a number of general purpose registers (from 8 to 64 registers) Computers usually have a number of general purpose registers (from 8 to 64 registers) Access to data in these registers is much faster than data stored in the main memory Access to data in these registers is much faster than data stored in the main memory -registers are already in the CPU -the number of registers is small; thus a few bits are needed to select which of the registers will take part in a given operation Because of fast access, registers are used to store data temporarily in the CPU during processing Because of fast access, registers are used to store data temporarily in the CPU during processing Example Example Move A,Ri Move Ri,A Add A,Ri Registers

25. 25 In some modern computers, such as the PowerPC, computations can be performed directly only on data held in the CPU registers In some modern computers, such as the PowerPC, computations can be performed directly only on data held in the CPU registers When a processor has several general purpose registers, many instructions involve only operands that are in the registers When a processor has several general purpose registers, many instructions involve only operands that are in the registers Add Ri, Rj Add Ri,Rj,Rk Register Transfer Notation Register Transfer Notation Registers (cont.)

26. 26 Executions of Instructions Example: C  [A] +[B] To begin executing the program, the address of the first instruction must be placed into the PC To begin executing the program, the address of the first instruction must be placed into the PC Then the CPU control circuits use the information in the PC to fetch and execute instructions, one at a time: straight-line sequencing Then the CPU control circuits use the information in the PC to fetch and execute instructions, one at a time: straight-line sequencing Von Neumann architecture Von Neumann architecture

27. 27 Sequential Statements Adding a Sequence of n Numbers

28. 28 Branching Example: adding a list of n numbers Instead of using a long list of Add instructions, it is possible to place a single add instruction in a program loop Instead of using a long list of Add instructions, it is possible to place a single add instruction in a program loop A loop causes a straight line sequence of instructions to be executed repeatedly A loop causes a straight line sequence of instructions to be executed repeatedly

29. 29 Sequential Statements Adding a Sequence of Numbers Loop Sum Loop

30. 30 Branch instruction: an instruction that loads a new value in the PC, resulting in an abrupt change in program sequencing Branch instruction: an instruction that loads a new value in the PC, resulting in an abrupt change in program sequencing  As a result, the CPU fetches and executes the instruction at the new address instead of the instruction at the location that follows the branch Conditional branch: causes a branch if the specified condition is satisfied Conditional branch: causes a branch if the specified condition is satisfied Example: Branch>0 Loop  Branching occurs only if the result of the immediately preceding instruction (i.e. the decremented value of R1) is greater than zero Branch Instructions

31. 31 Condition Flags The processor keeps track of some information about the results of various operations for use by subsequent conditional branch instructions The processor keeps track of some information about the results of various operations for use by subsequent conditional branch instructions This information is recorded into bits called condition code flags This information is recorded into bits called condition code flags In some processors, the flags are grouped in a register called the condition or status register In some processors, the flags are grouped in a register called the condition or status register NZVC

32. 32 Common Condition Flags N (negative) N (negative)  1 if the result is negative, otherwise 0 Z (zero) Z (zero)  1 if the result is zero, otherwise 0 V (overflow) V (overflow)  1 if arithmetic overflow occurs, otherwise 0 C (carry) C (carry)  1 if a carry out results from the operation, otherwise 0 Some computers provide special test instructions that examines a value in a register or in main memory and sets or clears the N and Z flags accordingly Some computers provide special test instructions that examines a value in a register or in main memory and sets or clears the N and Z flags accordingly NZVC