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Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-2.

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Presentation on theme: "Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-2."— Presentation transcript:

1 Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-2

2 Outline Information of literature Background FPGA Design Flow Logic Synthesis Binary Decision Diagram (BDD) Power-Aware Logic Synthesis Comparison Conclusion 2

3 Information of literature Power-Aware FPGA Logic Synthesis Using Binary Decision Diagrams Kevin Oo Tinmaung, David Howland, and Russell Tessier February 2007 FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays 3

4 Background Performance-oriented Design Flow Low Power High Speed Methods to achieve these goals Materials (Si,Ge have different threshold) Devices (xMOS, FET, Bipolar) Place and Route (longer route means larger delay) Synthesis Algorithm System Design (SW/HW partition) 4

5 FPGA Design Flow Behavioral synthesis RTL synthesis Logic synthesis HDL RTL Boolean Circuit Placement Routing Final Chip 5

6 Logic Synthesis Optimization Boolean Function Mapping Circuit base on LUT Timing-Aware Area-Aware Power-Aware 6

7 Binary Decision Diagram 1/2 F=ab+cd a b c d 10 a b c d 10 Variables could be reordered. 7

8 Binary Decision Diagram 2/2 a b c d 10 F=ab+cdG=ab a b 10 H=cd c d 10 F=G+H G H 10 8

9 Power-Aware Logic Synthesis 1/2 9 (1 ) (2) Transition Density (D): the average number of transitions per unit time. Static Probability (P): the probability of the signal being high for a certain time period. Lower switching activity means lower dynamic power and lower short circuit power

10 Power-Aware Logic Synthesis 2/2 10 D (G) = P (G/a) *D (a) + P (G/b) *D (b) = P (b ⊕ 0) * D (a) + P (a ⊕ 0) * D (b) = P (b) *D (a) + P (a) *D (b) = 0.5*0.5 + 0.5*0.6 = 0.55 P (G) = P (a=1,b=1) = P (a) *P (b) = 0.5*0.5 = 0.25

11 Comparison SIS Flow (Berkeley)Power-Aware BDD Flow LUTsMax Delay (nS) Energy@ 50MHz (nJ) LUTsMax Delay (nS) Energy@ 50MHz (nJ) Average Power Consumption on benchmarks 18588.381.3916299.33 (111%) 1.20 (87%) 11

12 Conclusion Power-aware BDD based Synthesis Algorithm could reduce power consumption. Power-aware BDD based Synthesis Algorithm may cause increase timing delay. Proposed method could be useful in low power design. 12

13 Question Thanks! 13

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