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EE 5340 Semiconductor Device Theory Lecture 21 – Spring 2011

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Presentation on theme: "EE 5340 Semiconductor Device Theory Lecture 21 – Spring 2011"— Presentation transcript:

1 EE 5340 Semiconductor Device Theory Lecture 21 – Spring 2011
Professor Ronald L. Carter

2 Test 2 – Tuesday 05Apr11 11 AM Room 129 ERB Covering Lectures 11 to19
Open book - 1 legal text or ref., only. You may write notes in your book. Calculator allowed A cover sheet will be included with full instructions. For examples see ©rlc L21-07Apr2011

3 npn BJT currents in the forward active region ©RLC
IC = JCAC IB=-(IE+IC ) JnE JnC IE = -JEAE JRB=JnE-JnC JpE JGC JRE JpC ©rlc L21-07Apr2011

4 E-M linking current model
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5 E-M linking current model (cont)
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6 E-M linking current model (cont)
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7 More non-ideal effects in BJTs
Base-width modulation (FA: xB changes with changes in VBC) Current crowding in 2-dim base High-level injection (minority carriers g.t. dopant - especially in the base). Emitter Bandgap narrowing (NE ~ density of states at cond. band. edge) Junction breakdown at BC junction ©rlc L21-07Apr2011

8 npn Base-width mod. (Early Effect)
Fig 9.15* ©rlc L21-07Apr2011

9 Base-width modulation (Early Effect, cont.)
Fig 9.16* ©rlc L21-07Apr2011

10 Emitter current crowding in base
Fig 9.21* ©rlc L21-07Apr2011

11 Interdigitated base fixes emitter crowding
Fig 9.23* ©rlc L21-07Apr2011

12 Base region high- level injection (npn)
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13 Effect of HLI in npn base region
Fig 9.17* ©rlc L21-07Apr2011

14 Effect of HLI in npn base region (cont)
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15 Effect of HLI in npn base region (cont)
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16 Emitter region high- level injection (npn)
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17 Effect of HLI in npn emitter region
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18 Effect of HLI in npn base region
Figs 9.18 and 9.19* ©rlc L21-07Apr2011

19 Bandgap narrowing effects
Fig 9.20* Replaces ni2 throughout ©rlc L21-07Apr2011

20 Junction breakdown at BC junction
Reach-through or punch-through when WCB and/or WEB become large enough to reduce xB to zero Avalanche breakdown when Emax at EB junction or CB junction reaches Ecrit. ©rlc L21-07Apr2011

21 Hybrid-pi circuit model
Adapted from linking current version of E-M model with parasitic Rs and CSubstr C-E branch is linking current B-E branch is the reduced B-E diode with diffusion (for and rev) resistance and capacitance and junction cap. B-C branch is the reduced B-C diode with diffusion (for and rev) resistance and capacitance and junction cap. ©rlc L21-07Apr2011

22 Hybrid-pi Circuit model
Fig 9.33* ©rlc L21-07Apr2011

23 Gummel-Poon Static npn Circuit Model
B RBB ILC IBR ICC - IEC = IS(exp(vBE/NFVt - exp(vBC/NRVt)/QB B’ ILE IBF RE E ©rlc L21-07Apr2011

24 Gummel-Poon Static npn Circuit Model
Intrinsic Transistor RC B RBB ILC IBR ICC - IEC = {IS/QB}* {exp(vBE/NFVt)-exp(vBC/NRVt)} B’ ILE IBF RE E ©rlc L21-07Apr2011

25 Gummel Poon npn Model Equations
IBF = ISexpf(vBE/NFVt)/BF ILE = ISEexpf(vBE/NEVt) IBR = ISexpf(vBC/NRVt)/BR ILC = ISCexpf(vBC/NCVt) QB = (1 + vBC/VAF + vBE/VAR )  {½ + [¼ + (BFIBF/IKF + BRIBR/IKR)]1/2 } ©rlc L21-07Apr2011

26 Charge components in the BJT
**From Getreau, Modeling the Bipolar Transistor, Tektronix, Inc. ©rlc L21-07Apr2011

27 Gummel Poon Base Resistance
If IRB = 0, RBB = RBM+(RB-RBM)/QB If IRB > 0 RB = RBM + 3(RB-RBM)(tan(z)-z)/(ztan2(z)) [1+144iB/(p2IRB)]1/2-1 z = (24/p2)(iB/IRB)1/2 From An Accurate Mathematical Model for the Intrinsic Base Resistance of Bipolar Transistors, by Ciubotaru and Carter, Sol.-St.Electr. 41, pp , 1997. RBB = Rbmin + Rbmax/(1 + iB/IRB)aRB ©rlc L21-07Apr2011

28 BJT Characterization Forward Gummel
iC RC iB RE RB vBEx vBC vBE + - vBCx= 0 = vBC + iBRB - iCRC vBEx = vBE +iBRB +(iB+iC)RE iB = IBF + ILE = ISexpf(vBE/NFVt)/BF + ISEexpf(vBE/NEVt) iC = bFIBF/QB = ISexpf(vBE/NFVt)/QB ©rlc L21-07Apr2011

29 Ideal F-G Data iC and iB (A) vs. vBE (V) N = 1  1/slope = 59.5 mV/dec
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30 BJT Characterization Reverse Gummel
iE RC iB RE RB vBCx vBC vBE + - vBEx= 0 = vBE + iBRB - iERE vBCx = vBC +iBRB +(iB+iE)RC iB = IBR + ILC = ISexpf(vBC/NRVt)/BR + ISCexpf(vBC/NCVt) iE = bRIBR/QB = ISexpf(vBC/NRVt)/QB ©rlc L21-07Apr2011

31 Ideal R-G Data iE and iB (A) vs. vBE (V) N = 1  1/slope = 59.5 mV/dec
©rlc L21-07Apr2011

32 References * Semiconductor Physics and Devices, 2nd ed., by Neamen, Irwin, Boston, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Muller and Kamins, John Wiley, New York, 1986. ©rlc L21-07Apr2011


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