1. PROPRIETARY INFORMATION GPRS Chipset Iota Analog Base Band

2. PROPRIETARY INFORMATION 2 APC, AFC, ADAC Timing Serial Port (TSP) Base Band Codec (BBC) Voice Band Codec (VBC) Monitoring ADC (MADC) Voltage Regulator (1.8V, 2.7V) (VREG) Base Band Serial Port (BSP) Micro-control Serial Port (USP) ClockGene (CKG) Voice Band Serial Port (VSP) SIM Card Regulator and Level Shifters 3V, 1.8V (SIMS) Voltage Reference Power-On Control (VRPC) Battery Charger Interface (BCI) Test Access Port (TAP) Internal Bus Controller (IBIC) System Overview INT2

3. PROPRIETARY INFORMATION 3 Block Description: Codecs Voice Band Codec (VBC) –Voice Coder/Decoder –Uplink: ADC converted samples sent to DSP speech coder –Downlink: DAC converted samples received from DSP –Programmable Gain, Volume Control and Side Tone

4. PROPRIETARY INFORMATION 4 Voice Band

5. PROPRIETARY INFORMATION 5 Base Band Codec (BBC) –Base band uplink and downlink paths –Uplink: Modulates burst data from DSP –Downlink: Converts I/Q data from RF to digital samples –Activity timing controlled by TPU of DBB –2 x 160-bit burst buffers for multislot capability Block Description: Codecs

6. PROPRIETARY INFORMATION 6 Baseband Uplink

7. PROPRIETARY INFORMATION 7 Baseband Downlink

8. PROPRIETARY INFORMATION 8 Block Description: Serial Ports Voice band serial port (VSP) Time Serial Port (TSP) –Control real time radio activation windows of Iota: –BUL/BDL power-on, calibration, TX/RX, and ADC startup –Processed by TPU in DBB –6.5 MHz serial clock Microcontroller Serial Port (USP) –3 terminal synchronous serial port (UDX, UDR, UEN) –13 MHz serial clock (from master clock) –Access to all internal register through IBC Base Band Serial Port –Bi-directional serial port with double buffered TX/RX, 13 MHz –Read/Write access of all internal registers through IBC –Format: 16-bit + Frame Sync

9. PROPRIETARY INFORMATION 9 Voice Band Serial Interface

10. PROPRIETARY INFORMATION 10 TSP Block Diagram Baseband UplinkBaseband DownlinkMADC Bit 6 : BULON : Power-on window of the baseband uplink Bit 5 : BULCAL : Offset calibration window of the baseband uplink. Bit 4 : BULENA : Transmission window of the basband uplink Bit 3 : BDLON : Power-on window of the baseband downlink Bit 2 : BDLCAL : Offset calibration window of the baseband downlink. Bit 1 : BDLENA : Transmission window of the basband downlink Bit 0 : STARTADC : Window for ADC conversion control

11. PROPRIETARY INFORMATION 11 USP Calypso Iota

12. PROPRIETARY INFORMATION 12 USP Data Format Writing to Internal Registers : –Bit 0: At zero it indicates a write operation. –Bit 1 to 5: This field shall contain the address of the register to be accessed. –Bit 6 to 15: This field shall contain the data to be written into the internal register. Reading from Internal Registers : –Bit 0: At one it indicates a read operation. –Bit 1 to 5: This field shall contain the address of the register to be accessed. –Bit 6 to 15: This filed don’ t care in a read request operation.

13. PROPRIETARY INFORMATION 13 Baseband Serial Port CalypsoIota

14. PROPRIETARY INFORMATION 14 Block Description: RF Control Automatic Power Control (APC) –Generate envelope signal for RF burst power ramp control –Supports single slot and multislot transmission with smooth power transitions between consecutive bursts at different power levels –Includes 10 bit DAC and RAM for digital storage of power ramp edge shapes of envelope signals –Timing is controlled by TSP signals

15. PROPRIETARY INFORMATION 15 2.167MHz,4x16 steps interpolation 16steps 5bits APC Control

16. PROPRIETARY INFORMATION 16 When SEL256128=1 When SEL256128=0 APC Control

17. PROPRIETARY INFORMATION 17 Automatic Frequency Control (AFC) –Controls GSM 13 MHz oscillator to synchronize with base station –DAC optimized for high resolution conversion using 13 bit accuracy Block Description: RF Control

18. PROPRIETARY INFORMATION 18 BSP or USP 25 KOhm 33 nF 0 ~ 2.4V AFC Control

19. PROPRIETARY INFORMATION 19 Block Description: MADC Monitoring ADC (MADC) –Consists of 10-bit ADC with 8 analog multiplexed inputs –4 internal inputs dedicated to monitoring: Main battery voltage Backup battery voltage Charger voltage Charger current –4 inputs externally accessible

20. PROPRIETARY INFORMATION 20 Block Description: VREG Voltage Regulation (VREG) –VRDBB - Programmable - (1.8V, 1.5V, 1.3V) for DBB core –VRIO - 2.8V supply for digital core and I/Os of Iota –VRMEM - 2.8V, 1.8V supply for external flash and DBB memory interface –VRRAM - 2.8V or 1.8V for SRAM and DBB memory interface –VRABB - 2.8V for Iota analog functions –VRSIM - 2.9V,1.8V for SIM and SIM drivers

21. PROPRIETARY INFORMATION 21 SIMS- Block Diagram SIM Card Level Shifters (SIMS) –Allows use of both 3V and 1.8V SIM card types

22. PROPRIETARY INFORMATION 22 Voltage Reference / Power On Control (VRPC) Block Description - providing internal references currents and voltages, internal clock. - checking of power supplies levels: batteries and LDO output voltages - detection of Switch ON condition, - controlling step by step Switch OFF to Switch ON logic sequence and Switch ON to Switch OFF logic sequence, - generation of interrupts. - generation of emergency Switch OFF request.

23. PROPRIETARY INFORMATION 23 VRPC (Voltage Reference Power-on Control) VREF RTC_ALARM ONNOFF IBIAS PWON PRWON INT1/INT2 RESPWRONZ REFGND TESTRESETZ VRPC - Pins Description

24. PROPRIETARY INFORMATION 24 Clock Generator Source: –Squared digital system master clock, CK13M, of 13Mhz. –CLK32K_OUT used by the DBB as reference clock for low power modes Target: –Serial Interfaces and the Bus Controller: CKUSP (13MHz), CKIBIC (13MHz), CKBSP (13MHz), CKTSP (13 MHz). –Baseband Codec: CKBDL (13 MHz) and CKBUL (4.3 MHz). –Auxiliary function: CKMADC (13 MHz), CKAPC (13 MHz) and CKAFC (4.3 MHz). –Voice Codec: CKVBC (13 MHz). –SIM Card Clock: CKSIM ( SCLK3 External Clock ) or OSCAS. –VREG Clock: CKVREG (13 MHz).

25. PROPRIETARY INFORMATION 25 LED drivers LEDA is dedicated for paging indication. LEDB is dedicated for LCD backlight and Keypad backlight. LEDC is dedicated for charging indication with hardware switch on.

26. PROPRIETARY INFORMATION 26 Block Description Test Access Port (TAP) –Meets JTAG test standard (IEEE 1131.1) –Allows JTAG instructions debug/test modes –4 pins: TDO, TDI, TCK, TMS Auxiliary DAC (ADAC) –General purpose 10-bit DAC Battery Charger Interface (BCI) –Support for 1-cell Li-Ion and 3-cell NiMH –MADC used for monitoring battery voltage, temperature, type, charge current, and charger input voltage –Voltage levels controlled by register accessible through BSP or USP

27. PROPRIETARY INFORMATION 27 Block Description Internal Bus and Interrupt Controller (IBIC) –Provides read/write access to all internal registers through BSP or USP –Arbitrates access to internal Iota bus and direct read data to the proper serial port

28. PROPRIETARY INFORMATION 28 Pinout Overview