1. PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1

2.  A numerical study on performance of MOSFET is analyzed. The drain current value of MOSFET can be reduced by varying substrate, gate and gate oxide materials. By reducing the drain current ( I d ), the power dissipation can be reduced. Thus the performance of the device can be increased by reducing the drain current ( I d ). 2

3.  Single gate MOSFET  Output characteristics  Transfer characteristics  On state Resistance  Power dissipation 3

4. 4

5. SUBSTRATE MATERIALS  Silicon  Germanium GATE MATERIAL  Aluminium GATE OXIDE MATERIALS  Silicon di oxide  Hafnium oxide  Air 5

6. I d =k n W/L((V gs -V T )V ds -(V ds 2 /2)) k n =C ox µ n Where I d – drain current k n - process parameter W-width of gate L-length of gate V gs – gate source voltage V T - threshold voltage V ds - drain source voltage C ox - gate oxide capacitance µ n - charge carrier effective mobility 6

7.  Output characteristics is a plot between drain voltage(V DS ) and drain current(I D ) by keeping gate voltage(V GS ) constant.  CUTOFF REGION: I D =0  LINEAR REGION : I D = µ n C 0x W/L ((V GS -V T )V DS -(V DS 2 /2)) 7

8. SATURATION REGION : I D =0.5 µ n C 0x W/L(V GS- V T ) 2 µ n – mobility C 0X – capacitance of oxide layer C 0X – (ε 0 ε r )/t 0x ε 0 –permittivity of free space ε 0 –8.854*10^-12 ε r –relative permittivity 8

9. 9 V ds (2V) I D (A) V ds (3V) I D (A) V ds (4V) I D (A) V ds (5V) I D (A) V ds (6V) I D (A) 05.01E-1705.61E-1706.21E-1701.09E-1608.17E-17 0.20.0002730.20.0004250.20.0005440.20.0006420.20.000725 0.40.0004620.40.0007780.40.0010260.40.001230.40.001403 0.60.0005540.60.0010290.60.0014140.60.0017330.60.002004 0.80.0005830.80.0011720.80.0016890.80.0021290.80.002506 1.00.00059510.00123210.00185310.00240710.002893 1.20.0006041.20.0012551.20.001931.20.0025751.20.003161 1.40.0006121.40.0012681.40.0019631.40.002661.40.003324 1.60.0006181.60.0012791.60.001981.60.0026981.60.00341 1.80.0006241.80.0012881.80.0019931.80.0027191.80.003451 20.0006320.00129620.00200420.00273320.003474

10. 10

11.  R ON = 1/(μ n C OX W/L)(V gs -V ds -V T ) μ n -charge carrier effective mobility C OX - gate oxide capacitance W –width of the gate L-length of the gate V gs – gate source voltage V T - threshold voltage V ds - drain source voltage 11

12. 12 I d (A)RON2(Ω)I d (A)RON3(Ω)I d (A)RON4(Ω)I d (A)RON5(Ω)I d (A)RON6(Ω) 5.01E-170 5.61E-1706.21E-1701.09E-1608.17E-170 0.000273733.8 0.000425470.630.000544367.7150.000642311.5540.000725275.686 0.000462865.636 0.000778514.0990.001026389.9660.00123325.3170.001403285.168 0.0005541082.27 0.001029582.8240.001414424.280.001733346.1820.002004299.353 0.0005831371.47 0.001172682.5010.001689473.5240.002129375.7280.002506319.184 0.0005951679.4 0.001232811.7410.001853539.6710.002407415.4460.002893345.674 0.0006041986.01 0.001255956.320.00193621.6070.002575466.0160.003161379.612 0.0006122288.94 0.0012681103.770.001963713.2890.00266526.3610.003324421.117 0.0006182587.96 0.0012791250.960.00198807.930.002698593.0560.00341469.205 0.0006242883.39 0.0012881397.340.001993902.9620.002719662.1150.003451521.612.000633175.55 0.0012961542.810.002004997.820.002733731.6760.003474575.788

13. 13

14. P D = I D 2 R ON I D = drain current R ON = ON state resistance 14

15. 15 I d (A)Pd2(W) I d (A)Pd3(W) I d (A)Pd4(W) I d (A)Pd5(W) I d (A)Pd6(W) 5.01E-1705.61E-1706.21E-1701.09E-1608.17E-170 0.0002735.45E-050.0004258.50E-050.0005440.0001090.0006420.0001280.0007250.000145 0.0004620.0001850.0007780.0003110.0010260.000410.001230.0004920.0014030.000561 0.0005540.0003330.0010290.0006180.0014140.0008480.0017330.001040.0020040.001203 0.0005830.0004670.0011720.0009380.0016890.0013520.0021290.0017030.0025060.002005 0.000595 0.001232 0.001853 0.002407 0.002893 0.0006040.0007250.0012550.0015060.001930.0023170.0025750.003090.0031610.003793 0.0006120.0008560.0012680.0017760.0019630.0027480.002660.0037240.0033240.004654 0.0006180.0009890.0012790.0020460.001980.0031690.0026980.0043170.003410.005456 0.0006240.0011240.0012880.0023190.0019930.0035880.0027190.0048930.0034510.006212 0.000630.001260.0012960.0025930.0020040.0040090.0027330.0054670.0034740.006947

16. 16

17.  Output characteristics is a plot between gate voltage (V GS ) and drain current(I D ) by keeping drain voltage(V DS ) constant 17

18. 18 Gate voltage(V)Drain current (A) 01.44E-11 0.26.74E-11 0.45.83E-09 0.67.36E-07 0.82.09E-05 18.30E-05 1.20.000171 1.40.000274 1.60.000386 1.80.000506 20.00063

19. 19

20.  “ HYBRID Ge-Si BASED MOSFET DEVICES” in the “International Journal of Electrical, Electronics and Computer System (IJEECS)”  “ VARIATION OF GATE MATERIALS FOR HYBRID GE-SI MOSFET” in the “International Journal of Nanotechnology and Application journal” 20

21.  “HYBRID AlGaAs-SI BASED MOSFET DEVICES” in the “IOSR Journal of vlsi and signal processing”  “TRI-GATE STRUCTURE TO REDUCE DRAIN CURRENT” in “International Journal Of Electrical, Electronics and Telecommunication Engineering Recent Science Publications” 21

22.  “ ANALYSING THE PERFORMANCE OF MOSFET BY VARYING THE SUBSTRATE MATERIALS” in “Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE)”  “COMPARATIVE STUDY ON THE PERFORMANCE OF MOSFET WITH GOLD AND SILVER AS GATE MATERIALS” in “IMPACT :International Journal of Research in Engineering & Technology ” 22

23.  We have obtained output characteristics, transfer characteristics, ON resistance, power dissipation for MOSFET by changing the substrate and gate materials.  Thus the power dissipation of MOSFET is reduced with the help of reducing the drain current and the performance of the device is increased through this. 23

24.  H. Iwai, Extended Abstracts 2008 8 th International Workshop on Junction Technology (IWJT '08) (Shanghai, China 2008 May 15-16, IEEE Press) p. 1. [DOI:10.1109/IWJT.2008.4540004].  International Technology Roadmap for Semiconductors (ITRS) 2007 Edition.  Available from: http://www.itrs.net/links/2007ITRS/Home2007.html.  B. Razavi, Design of Analog CMOSIntegrated Circuits (McGraw-Hill, Boston,MA, 2001).  R. F. Pierret, Semiconductor Device Fundamentals (Addison- Wesley, Reading,MA, 1996) p. 691. 24

25.  J. Appenzeller et al., “Scheme for the fabrication of ultrashort channel MOSFETs,” Appl. Phys. Lett., vol. 77, pp. 298–300, July 2000  B. Yu et al., “15 nm gate length planar CMOS transistor,” in IEDM Tech.Dig., 2001, pp. 937–939. 25