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Reducing Test Application Time Through Test Data Mutation Encoding Sherief Reda and Alex Orailoglu Computer Science Engineering Dept. University of California,

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Presentation on theme: "Reducing Test Application Time Through Test Data Mutation Encoding Sherief Reda and Alex Orailoglu Computer Science Engineering Dept. University of California,"— Presentation transcript:

1 Reducing Test Application Time Through Test Data Mutation Encoding Sherief Reda and Alex Orailoglu Computer Science Engineering Dept. University of California, San Diego

2 Outline Introduction Test Data Mutation Encoding Time Reduction Analysis Experimental Results Conclusions Motivation Scheme overview Overlap exploration Computational aspects Hardware challenges Don’t care handling

3 Introduction Advancements in VLSI device fabrication  Unprecedented integration levels Increased test application time hinders volume manufacturing in today’s demanding market. High integration manufacturing  Increased test application time Testing multiple cores on System-on-a-Chip (SoC)  Increased test application time

4 Motivation 0 1 X 1 X X X X 1 1 0 X X 1 X 1 TDI LFSR TDO X 0 X 1 X 0 1 X X 0 X X 1 X 0 X Scan chain length Test time increase Flip Mutation reduces test time by specifying only the bits to be flipped Problem: Test responses destroy the scan cells’ content! Test Vector I Test Vector II Mutate

5 Decompose scan chain 0 X X 1 1 X 1 1 1 X X X 1 0 X X Large test vectors are transformed into small horizontal test slices Motivation 0 1 X 1 X X X X 1 1 0 X X 1 X 1 TDI LFSR TDO 0111XXX0X1XX11XX Scan chain length Bits to specify inversion Small test slice Small number of bits to specify an inversion

6 Motivation 0 1 X 1 X X X X 1 1 0 X X 1 X 1 TDI LFSR TDO Decompose scan chain 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 Large test vectors are transformed into small horizontal test slices Scan chain length Bits to specify inversion Small test slice Small number of bits to specify an inversion

7 Test Data Mutation Encoding TDO 2x4 Decoder TDI DSR Flip DOR ENABLE MISR CLK 00 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 TDI: Test Data Input DSR: Decoder Shift Register DOR: Decoder Output Register TDO: Test Data Output 0(00)1(01)2(10)3(11) 1 1 0 0 Mutated Test Slice Bits 2 & 3 need to be flipped 10, 11 to be injected = 4 bits Overlap can reduce this to just 11 = 2 bits 0011011

8 Test Data Mutation Encoding 2x4 Decoder TDI DSR Flip DOR ENABLE MISR TDO CLK 01 0 0 1 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 0 Mutated Test Slice TDI: Test Data Input DSR: Decoder Shift Register DOR: Decoder Output Register TDO: Test Data Output Bits 2 & 3 need to be flipped 10, 11 to be injected = 4 bits Overlap can reduce this to just 11 = 2 bits 0(00)1(01)2(10)3(11) 001101

9 Test Data Mutation Encoding TDO 2x4 Decoder TDI DSR Flip DOR ENABLE MISR CLK 11 0 0 1 1 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 0 Mutated Test Slice TDI: Test Data Input DSR: Decoder Shift Register DOR: Decoder Output Register TDO: Test Data Output Bits 2 & 3 need to be flipped 10, 11 to be injected = 4 bits Overlap can reduce this to just 11 = 2 bits 0(00)1(01)2(10)3(11) 00110

10 Test Data Mutation Encoding 2x4 Decoder TDI DSR Flip DOR ENABLE MISR TDO CLK 11 1 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 Mutated Test Slice TDI: Test Data Input DSR: Decoder Shift Register DOR: Decoder Output Register TDO: Test Data Output 0(00)1(01)2(10)3(11) 0011

11 Test Data Mutation Encoding 2x4 Decoder TDI DSR Flip DOR ENABLE MISR TDO CLK 11 1 0 1 0 1 1 0 1 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 0 1 1 0 Mutated Test Slice TDI: Test Data Input DSR: Decoder Shift Register DOR: Decoder Output Register TDO: Test Data Output 0(00)1(01)2(10)3(11) 001

12 Test Data Mutation Encoding 2x4 Decoder TDI DSR Flip DOR ENABLE MISR TDO CLK 01 1 0 1 1 1 1 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 0 1 1 0 Mutated Test Slice TDI: Test Data Input DSR: Decoder Shift Register DOR: Decoder Output Register TDO: Test Data Output 0(00)1(01)2(10)3(11) 00

13 Test Data Mutation Encoding 2x4 Decoder TDI DSR Flip DOR ENABLE MISR TDO CLK 01 1 0 0 1 1 1 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 0 1 1 1 Mutated Test Slice TDI: Test Data Input DSR: Decoder Shift Register DOR: Decoder Output Register TDO: Test Data Output 0(00)1(01)2(10)3(11) 0

14 Test Data Mutation Encoding 2x4 Decoder TDI DSR Flip DOR ENABLE MISR TDO CLK 01 1 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 0 1 1 1 Mutated Test Slice 7 clock cycles are needed to inject 21 bits through 3 parallel streams to mutate the test vector. 57% reduction in test application time TDI: Test Data Input DSR: Decoder Shift Register DOR: Decoder Output Register TDO: Test Data Output 0(00)1(01)2(10)3(11)

15 Fundamental Challenges Input test data indicates flips needed to mutate test slices. Optimal ordering of the indices  maximal overlap  minimal test application time. Problem: What is the flipping order that attains the minimal number of clock cycles? Input test data encodes the indices of flip locations.

16 Overlap Exploration 000 100 1 0 000 3x8 Decoder MISR TDO TDI

17 000 100 110 010 0 1 0 1 100 3x8 Decoder MISR TDO TDI Overlap Exploration

18 000 100 110 111 011 101 010 001 State Transition Diagram of DSR (DeBruijn Diagram) 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 011 3x8 Decoder MISR TDO TDI 4 1 2 5 6 7 3 0 Overlap Exploration

19 000 100 110 111 011 101 010 001 State Transition Diagram of DSR (DeBruijn Diagram) 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0123 4 5 6 7 0 1 2 3 4 5 6 7 Distance Matrix 03231323 10231323 21032123 21202123 32120212 32323012 32313201 32313230 Objective: Mutating an 8 bit test slice through flipping bits 2 & 6 4 1 2 5 6 7 3 0 Overlap Exploration

20 000 100 110 111 011 101 010 001 State Transition Diagram of DSR (DeBruijn Diagram) 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 Objective: Mutating an 8 bit test slice through flipping bits 2 & 6 0123 4 5 6 7 0 1 2 3 4 5 6 7 Distance Matrix 03231323 10231323 21032123 21202123 32120212 32323012 32313201 32313230 First option: 4-2-6 yields 3 clock cycles 4 1 2 5 6 7 3 0 Overlap Exploration

21 000 100 110 111 011 101 010 001 State Transition Diagram of DSR (DeBruijn Diagram) 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 Objective: Mutating an 8 bit test slice through flipping bits 2 & 6 0123 4 5 6 7 0 1 2 3 4 5 6 7 Distance Matrix 03231323 10231323 21032123 21202123 32120212 32323012 32313201 32313230 Second option: 4-6-2 yields 4 clock cycles 4 1 2 5 6 7 3 0 Overlap Exploration

22 Computational Aspects Optimal number of test bits  Enumerating all the possible trips to pick the one that achieves the minimal total distance If there are n bits to flip, then there are n! trips to consider in order to calculate the optimal trip Large number of flips  Enumeration of all trips is computationally infeasible  A greedy strategy is utilized

23 000 100 110 111 011 101 010 001 Greedy strategy is applied to visit the three states 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 Greedy strategy - Repeat until the test slice is mutated: Move from the current state to the closest next state corresponding to the bit index to be flipped - Move from the initial state to the closest state. Objective: Mutating an 8 bit test slice through flipping bits 5, 6 & 7 4 1 2 5 6 7 3 0 Computational Aspects

24 000 100 110 111 011 101 010 001 Greedy strategy is applied to visit the three states 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 Greedy strategy - Repeat until the test slice is mutated: Move from the current state to the closest next state corresponding to the bit index to be flipped - Move from the initial state to the closest state. Objective: Mutating an 8 bit test slice through flipping bits 5, 6 & 7 4 1 2 5 6 7 3 0 Computational Aspects

25 000 100 110 111 011 101 010 001 Greedy strategy is applied to visit the three states 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 Greedy strategy - Repeat until the test slice is mutated: Move from the current state to the closest next state corresponding to the bit index to be flipped - Move from the initial state to the closest state. Objective: Mutating an 8 bit test slice through flipping bits 5, 6 & 7 4 1 2 5 6 7 3 0 Computational Aspects

26 000 100 110 111 011 101 010 001 Greedy strategy is applied to visit the three states 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 Greedy strategy - Repeat until the test slice is mutated: Move from the current state to the closest next state corresponding to the bit index to be flipped - Move from the initial state to the closest state. Objective: Mutating an 8 bit test slice through flipping bits 5, 6 & 7 4 1 2 5 6 7 3 0 Computational Aspects

27 Don’t Care Handling Test Slice A Test Slice B Test Slice C Test Slice D 11100110 x0xxx0xx xxxxxxxx 76543210 xxxxxxxx 1x0xx0xx Test Slice E

28 Don’t Care Handling Test Slice A Test Slice B Test Slice C Test Slice D Test Slice E 11100110 x0xxx0xx xxxxxxxx 76543210 xxxxxxxx 1x0xx0xx There are 2 cases: A run of don’t cares in between two identical specified bits A run of don’t cares in between two distinctly specified bits

29 Don’t Care Handling Test Slice A Test Slice B Test Slice C Test Slice D Test Slice E 11100110 10xxx0xx 1xxxxxxx 76543210 1xxxxxxx 1x0xx0xx There are 2 cases: A run of don’t cares in between two identical specified bits A run of don’t cares in between two distinctly specified bits

30 Don’t Care Handling Assume we have the 3 test slices. 11100110 x0xxx0xx 0x0xxxxx 11100110 Test Slice A Test Slice B Test Slice C 76543210 x0xxx0xx 0x0xxxxx 6 clock cycle 10100010 00000010 000 100 110 111 011 101 010 001 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 AB 3 Clock Cycles 4 1 2 5 6 7 3 0

31 Don’t Care Handling Assume we have the 3 test slices. 11100110 76543210 6 clock cycle 10100010 00000010 000 100 110 111 011 101 010 001 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 BC 3 Clock Cycles 11100110 x0xxx0xx 0x0xxxxx Test Slice A Test Slice B Test Slice C 76543210 4 1 2 5 6 7 3 0

32 11100110 10000010 00000010 4 clock cycles 76543210 While mutating test slice A to test slice B we can flip bit 5 in anticipation for test slice C. This saves 2 bits in mutating test slice B to C. Don’t Care Handling 000 100 110 111 011 101 010 001 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 4 1 2 5 6 7 3 0 Assume we have the 3 test slices. 11100110 x0xxx0xx 0x0xxxxx Test Slice A Test Slice B Test Slice C 76543210 AB 3 Clock Cycles

33 11100110 10000010 00000010 4 clock cycles 76543210 While mutating test slice A to test slice B we can flip bit 5 in anticipation for test slice C. This saves 2 bits in mutating test slice B to C. Don’t Care Handling 000 100 110 111 011 101 010 001 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 4 1 2 5 6 7 3 0 Assume we have the 3 test slices. 11100110 x0xxx0xx 0x0xxxxx Test Slice A Test Slice B Test Slice C 76543210 BC 1 Clock Cycle

34 Reducing I/O Pin Requirements TDO/Enable To alleviate the requirement of adding an extra ENABLE pin, one of the I/O pins can be multiplexed or the TDO can be multiplexed. TDI MISR v Control v Enable TDO CLK 2x4 decoder

35 How many scan chains should the original scan chain be decomposed into? What is the decoder size to be used? What is the attainable time reduction for various scan chain configurations? What is the relation between the number of flips to be performed in mutating test slices and the achievable time reduction? Fundamental Issues

36 Outline Introduction Test Data Mutation Encoding Time Reduction Analysis Experimental Results Conclusions Motivation Scheme overview Overlap exploration Computational aspects Hardware requirements Don’t care handling

37 Time Reduction Analysis 000 100 110 111 011 101 010 001 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 Initial State 0 0 0 Shifts New Reachable States Next State 01 000 1 X001 2 XX0 2 3 XXX 4 If we only need to flip one bit to mutate the current test slice to the next test slice, how many shift clock cycles are needed? 000 3x8 Decoder MISR TDO TDI Hardware Organization State transition diagram of the decoder shift register 0 0 1 001 01 X00 1 2 XX0 2 2 XXX 3 3 Weighted average shifts for state 000: 2.125 cycles Weighted average shifts for state 001: 1.875 cycles

38 The average number of clock cycles needed to reach a combination of states is not only function of the initial state but also of the particular combination of states to be visited. Time Reduction Analysis Given an initial state, what is the average number of clock cycles needed to reach a different state? 1.84 clock cycles.

39 Test Slice Size Time Reduction Analysis In general, what is the average number of clock cycles needed to mutate the test slices of various sizes?

40 Test Slice Size Time Reduction Analysis Test Slice Size Time Reduction Ratio = Test Slice Size Average number of shift clock cycles

41 Test Slice Size In this experiment, we assume that the number of bits to be flipped to mutate a 32 bit test slice is 8 times the number of bits to be flipped to mutate a 4 bit slice. Time Reduction Analysis Bits to Flip x Test slice size/4

42 Experimental Results Compressing MinTest vectors results in an average time reduction ratio of 2.4 for the 5 benchmark circuits MinTest: Hamzaoglu & Patel, ITC, 1998 Virtual Scan Chains: Jas & Touba, VTS, 2000 Golomb Coding: Chandra & Chakrabarty, VTS, 2000 Test Data Mutation using MinTest fully specified vectors MinTest fully specified vectors are compressed using test data mutation

43 Experimental Results Compressing the incompletely specified test vectors, using last flip heuristic, results in an average time reduction ratio of 6.7 in comparison with MinTest for the 5 benchmark circuits MinTest: Hamzaoglu & Patel, ITC, 1998 Test Data Mutation using MinTest fully specified vectors Test Data Mutation using incompletely specified vectors Test Data Mutation is applied to incompletely specified test vectors obtained from Atalanta

44 Experimental Results Augmenting Scan Chain Concealment results in an increased test time reduction by a factor of 1.8 Scan Chain Concealment: Bayraktaroglu, Orailoglu, DAC, 2001 Test Data Mutation using scan chain concealment fully specified vectors

45 Conclusions A new methodology to reduce test application time through test data mutation is presented Thorough analysis of the proposed method identifies configurations and conditions for optimal test time reduction Reduced hardware overhead Experimental results on ISCAS’89 benchmarks confirm drastic test time application reductions Effective overlapping of test data yields huge reductions in test application time

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