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REAL TIME FACE DETECTION
Justin Rilling Pooja Mhapsekar Moinuddin Sayed Ogom J Obinor
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Introduction The idea is to be able to detect faces appearing in an image. The faces can be of different sizes and orientations. The motivation behind implementing this on an FPGA is that image processing is inherently parallel in nature and lends itself well to an FPGA.
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Viola and Jones’ Detector
Key Contributions 1. Integral Image – fast computation of features used by the detector. 2. Combines complex classifiers in “cascade” – focus on facial features.
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Integral Image Major contribution of the Viola and Jones detector.
Summation of pixel values of the original image. Value at location (x,y) = sum of values of pixels above and to the left of (x,y). Whole image converted to integral image and a window buffer used to scan the entire image.
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Haar Classifiers Classifiers are composed of 2-3 rectangles.
Weights and sizes associated with features – obtained through AdaBoost. Classifier sum = ∑ (area * weights) Integral image makes area calculation easy. Area = L4–L3–L2+L1. Several classifiers compose a stage.
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Stage Sum of all Haar feature classifiers compared with the stage threshold. Multiple stages, each stage has different number of classifiers. Threshold obtained from AdaBoost algorithm.
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Face Detection Example
Stage Number Classifier Number Classifier Sum Classifier Threshold < 0.0 0.0 Right Value 0.0 Stage Threshold Stage Sum + < 0.0 0.0 Left Value 0.0 1
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Face Detection Example
Stage Number Classifier Number Classifier Sum Classifier Threshold < 426 542 Right Value Stage Threshold Stage Sum + < 0.0 Left Value 1
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Face Detection Example
Stage Number Classifier Number Classifier Sum Classifier Threshold < 426 542 Right Value Stage Threshold Stage Sum + < Left Value 1
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Face Detection Example
Stage Number Classifier Number 1 Classifier Sum Classifier Threshold < 887 2045 Right Value Stage Threshold Stage Sum + < Left Value 1
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Face Detection Example
Stage Number Classifier Number 1 Classifier Sum Classifier Threshold < 887 2045 Right Value Stage Threshold Stage Sum + < Left Value 1
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Face Detection Example
Stage Number Classifier Number 2 Classifier Sum Classifier Threshold < 349 568 Right Value Stage Threshold Stage Sum + < Left Value 1
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Face Detection Example
Stage Number Classifier Number 2 Classifier Sum Classifier Threshold < 349 568 Right Value Stage Threshold Stage Sum + < Left Value 1
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Face Detection Example
Stage Number Classifier Number 2 Classifier Sum Classifier Threshold < 349 568 Right Value Stage Threshold Stage Sum + < Left Value 1 Window Buffer Failed Stage 0
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Face Detection Example
Stage Number Classifier Number Classifier Sum Classifier Threshold < 0.0 0.0 Right Value 0.0 Stage Threshold Stage Sum + < 0.0 0.0 Left Value 0.0 1
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Face Detection Example
Stage Number Classifier Number Classifier Sum Classifier Threshold < 0.0 0.0 Right Value 0.0 Stage Threshold Stage Sum + < 0.0 0.0 Left Value 0.0 1
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Face Detection Example
Stage Number Classifier Number Classifier Sum Classifier Threshold < 0.0 0.0 Right Value 0.0 Stage Threshold Stage Sum + < 0.0 0.0 Left Value 0.0 1
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Face Detection Example
Stage Number Classifier Number Classifier Sum Classifier Threshold < 0.0 0.0 Right Value 0.0 Stage Threshold Stage Sum + < 0.0 0.0 Left Value 0.0 1
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Face Detection Example
Stage Number Classifier Number Classifier Sum Classifier Threshold < 0.0 0.0 Right Value 0.0 Stage Threshold Stage Sum + < 0.0 0.0 Left Value 0.0 1
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Face Detection Example
Stage Number Classifier Number Classifier Sum Classifier Threshold < 0.0 0.0 Right Value 0.0 Stage Threshold Stage Sum + < 0.0 0.0 Left Value 0.0 1
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Face Detection Example
Stage Number Classifier Number Classifier Sum Classifier Threshold < 0.0 0.0 Right Value 0.0 Stage Threshold Stage Sum + < 0.0 0.0 Left Value 0.0 1
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Top Level Design Get Image Get Scaled Image Get Integral Image
Window Buffer (21x21) Draw Rectangle If face is det. End of Image? Face Detection Pipeline YES Monitor NO
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Face Detection Pipeline
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Original End Product USB Webcam FPGA Display USB DVI
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Updated End Product FPGA Display DVI Digital Interface
1/3 Color Camera Mod C3188A-6018 Supports several standard image data formats including YCrCb 4:2:2 640 x 480 resolution 5 V signaling 30 fps
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Updated End Product XC95144XL CPLD FPGA 5 V Signaling 3.3 V Signaling
DVI 1/3 Color Camera Mod C3188A-6018 Supports several standard image data formats including YCrCb 4:2:2 640 x 480 resolution 5 V signaling 30 fps Display
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DVI Controller
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Questions ??? References:
P. Viola and M. Jones, “Robust real-time object detection,” International Journal of Computer Vision, 57(2), , 2004. Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner, “FPGA-Based Face Detection System Using Haar Classifiers,” Proceeding of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, , 2009.
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OpenCV Program – Lena.jpg
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OpenCV Program – ER.jpg
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OpenCV Program – ER.jpg Window Buffer (2, 152, 122)
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Face Detection Pipeline
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OpenCV Program – ER.jpg Window Buffer (3, 165, 20)
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Face Detection Pipeline
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Questions ???
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